Project Settings
Project Name proj_1 Implementation Name proyecto_global
Top Module esquema_global Pipelining 1
Retiming 0 Resource Sharing 1
Fanout Guide 1000 Disable I/O Insertion 0
Disable Sequential Optimizations 0 Clock Conversion 1

Run Status
Job Name Status CPU Time Real Time Memory Date/Time
(compiler)Complete 30 98 0 - 0m:01s - 27/09/2017
5:40:49
(premap)Complete 2 4 0 0m:00s 0m:00s 141MB 27/09/2017
5:40:51
(fpga_mapper)Complete 16 11 0 0m:01s 0m:01s 145MB 27/09/2017
5:40:53
Multi-srs Generator Complete27/09/2017
5:40:50

Area Summary
Register bits 72 I/O cells 25
Block RAMs (v_ram) 0 DSPs (dsp_used) 0
ORCA LUTs (total_luts) 44

Timing Summary
Clock NameReq FreqEst FreqSlack
divfrec1|tdataout20_derived_clock2.1 MHzNANA
esquema_global|N_25_inferred_clock2.1 MHz201.0 MHz475.795
esquema_global|N_38_inferred_clock1.0 MHz165.2 MHz993.946
esquema_global|clk_ext_sal1.0 MHz254.8 MHz996.075
pll1|CLKOS3_inferred_clock1.0 MHz343.8 MHz997.091
System1.0 MHz1.9 MHz480.664

Optimizations Summary
Combined Clock Conversion 2 / 3