Project Settings
Project Name proj_1 Implementation Name proyecto_global
Top Module esquema_global Pipelining 1
Retiming 0 Resource Sharing 1
Fanout Guide 1000 Disable I/O Insertion 0
Disable Sequential Optimizations 0 Clock Conversion 1

Run Status
Job Name Status CPU Time Real Time Memory Date/Time
(compiler)Complete 26 78 0 - 0m:01s - 21/09/2017
7:05:51
(premap)Complete 2 3 0 0m:00s 0m:00s 141MB 21/09/2017
7:05:53
(fpga_mapper)Complete 13 9 0 0m:01s 0m:01s 145MB 21/09/2017
7:05:55
Multi-srs Generator Complete21/09/2017
7:05:53

Area Summary
Register bits 54 I/O cells 25
Block RAMs (v_ram) 0 DSPs (dsp_used) 0
ORCA LUTs (total_luts) 28

Timing Summary
Clock NameReq FreqEst FreqSlack
esquema_global|N_25_inferred_clock2.1 MHz201.0 MHz475.795
pll2|CLKOS3_inferred_clock1.0 MHz334.2 MHz997.007
pll2|CLKOS_inferred_clock1.0 MHz178.8 MHz994.408
System1.0 MHz1.9 MHz480.664

Optimizations Summary
Combined Clock Conversion 0 / 3