Synthesis Report #Build: Synplify Pro L-2016.03L-1, Build 097R, Jul 4 2016 #install: C:\lscc\diamond\3.8\synpbase #OS: Windows 8 6.2 #Hostname: RORDRIGO # Thu Sep 21 05:01:53 2017 #Implementation: proyecto_global Synopsys HDL Compiler, version comp2016q2rc, Build 192R, built Jul 5 2016 @N|Running in 64-bit mode Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Synopsys VHDL Compiler, version comp2016q2rc, Build 192R, built Jul 5 2016 @N|Running in 64-bit mode Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. @N: CD720 :"C:\lscc\diamond\3.8\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns @N:"C:\TFG\exp1\control_disp.vhd":5:7:5:18|Top entity is set to control_disp. VHDL syntax check successful! At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 69MB peak: 70MB) Process completed successfully. # Thu Sep 21 05:01:53 2017 ###########################################################] Synopsys Verilog Compiler, version comp2016q2rc, Build 192R, built Jul 5 2016 @N|Running in 64-bit mode Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. @I::"C:\lscc\diamond\3.8\synpbase\lib\lucent\machxo2.v" (library work) @I::"C:\lscc\diamond\3.8\synpbase\lib\lucent\pmi_def.v" (library work) @I::"C:\lscc\diamond\3.8\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__) @I::"C:\lscc\diamond\3.8\synpbase\lib\vlog\umr_capim.v" (library snps_haps) @I::"C:\lscc\diamond\3.8\synpbase\lib\vlog\scemi_objects.v" (library snps_haps) @I::"C:\lscc\diamond\3.8\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps) @I::"C:\TFG\exp1\proyecto_global\esquema_global.v" (library work) Verilog syntax check successful! At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 69MB peak: 70MB) Process completed successfully. # Thu Sep 21 05:01:54 2017 ###########################################################] @I::"C:\lscc\diamond\3.8\synpbase\lib\lucent\machxo2.v" (library work) @I::"C:\lscc\diamond\3.8\synpbase\lib\lucent\pmi_def.v" (library work) @I::"C:\lscc\diamond\3.8\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__) @I::"C:\lscc\diamond\3.8\synpbase\lib\vlog\umr_capim.v" (library snps_haps) @I::"C:\lscc\diamond\3.8\synpbase\lib\vlog\scemi_objects.v" (library snps_haps) @I::"C:\lscc\diamond\3.8\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps) @I::"C:\TFG\exp1\proyecto_global\esquema_global.v" (library work) Verilog syntax check successful! File C:\TFG\exp1\proyecto_global\esquema_global.v changed - recompiling @N: CG364 :"C:\lscc\diamond\3.8\synpbase\lib\lucent\machxo2.v":49:8:49:11|Synthesizing module AND3 in library work. @N: CG364 :"C:\lscc\diamond\3.8\synpbase\lib\lucent\machxo2.v":43:7:43:10|Synthesizing module AND2 in library work. @N: CG364 :"C:\lscc\diamond\3.8\synpbase\lib\lucent\machxo2.v":563:7:563:9|Synthesizing module INV in library work. @N: CG364 :"C:\lscc\diamond\3.8\synpbase\lib\lucent\machxo2.v":56:8:56:11|Synthesizing module AND4 in library work. @N: CG364 :"C:\lscc\diamond\3.8\synpbase\lib\lucent\machxo2.v":857:7:857:8|Synthesizing module OB in library work. @N: CG364 :"C:\lscc\diamond\3.8\synpbase\lib\lucent\machxo2.v":498:7:498:8|Synthesizing module IB in library work. @N: CG364 :"C:\lscc\diamond\3.8\synpbase\lib\lucent\machxo2.v":1120:7:1120:9|Synthesizing module VHI in library work. @N: CG364 :"C:\lscc\diamond\3.8\synpbase\lib\lucent\machxo2.v":1793:7:1793:10|Synthesizing module OSCH in library work. @N: CG364 :"C:\TFG\exp1\proyecto_global\esquema_global.v":3:7:3:20|Synthesizing module esquema_global in library work. @N: CG794 :"C:\TFG\exp1\proyecto_global\esquema_global.v":66:13:66:15|Using module control_disp from library work @N: CG794 :"C:\TFG\exp1\proyecto_global\esquema_global.v":69:16:69:18|Using module cont_50mhz_1mhz from library work @W: CG781 :"C:\TFG\exp1\proyecto_global\esquema_global.v":69:16:69:18|Input Aclr on instance I52 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. @N: CG794 :"C:\TFG\exp1\proyecto_global\esquema_global.v":70:5:70:7|Using module pll1 from library work @N: CG794 :"C:\TFG\exp1\proyecto_global\esquema_global.v":86:9:86:11|Using module cont_BCD from library work @N: CG794 :"C:\TFG\exp1\proyecto_global\esquema_global.v":89:9:89:10|Using module divfrec1 from library work @N: CG794 :"C:\TFG\exp1\proyecto_global\esquema_global.v":116:9:116:11|Using module DEC_DISP from library work At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 70MB peak: 71MB) Process completed successfully. # Thu Sep 21 05:01:54 2017 ###########################################################] @N: CD720 :"C:\lscc\diamond\3.8\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns @N:"C:\TFG\exp1\control_disp.vhd":5:7:5:18|Top entity is set to control_disp. File Dependency file is up to date. It will not be rewritten. VHDL syntax check successful! @N: CD630 :"C:\TFG\exp1\DECODIF.vhd":4:7:4:14|Synthesizing work.dec_disp.dec_disp_arch. Post processing for work.dec_disp.dec_disp_arch @N: CD630 :"C:\TFG\exp1\divfrec1.vhd":14:7:14:14|Synthesizing work.divfrec1.structure. Post processing for work.divfrec1.structure @N: CD630 :"C:\TFG\exp1\cont_BCD.vhd":14:7:14:14|Synthesizing work.cont_bcd.structure. Post processing for work.cont_bcd.structure @N: CD630 :"C:\TFG\exp1\pll1.vhd":14:7:14:10|Synthesizing work.pll1.structure. Post processing for work.pll1.structure @N: CD630 :"C:\TFG\exp1\cont_50mhz_1mhz.vhd":14:7:14:21|Synthesizing work.cont_50mhz_1mhz.structure. Post processing for work.cont_50mhz_1mhz.structure @N: CD630 :"C:\TFG\exp1\control_disp.vhd":5:7:5:18|Synthesizing work.control_disp.control_arch. Post processing for work.control_disp.control_arch At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 70MB peak: 72MB) Process completed successfully. # Thu Sep 21 05:01:54 2017 ###########################################################] Synopsys Netlist Linker, version comp2016q2rc, Build 192R, built Jul 5 2016 @N|Running in 64-bit mode File C:\TFG\exp1\proyecto_global\synwork\layer0.srs changed - recompiling File C:\TFG\exp1\proyecto_global\synwork\layer1.srs changed - recompiling @W: Z198 :"C:\TFG\exp1\divfrec1.vhd":211:4:211:9|Unbound component ROM16X1A of instance LUT4_7 @W: Z198 :"C:\TFG\exp1\divfrec1.vhd":216:4:216:9|Unbound component ROM16X1A of instance LUT4_6 @W: Z198 :"C:\TFG\exp1\divfrec1.vhd":221:4:221:9|Unbound component ROM16X1A of instance LUT4_5 @W: Z198 :"C:\TFG\exp1\divfrec1.vhd":226:4:226:9|Unbound component ROM16X1A of instance LUT4_4 @W: Z198 :"C:\TFG\exp1\divfrec1.vhd":231:4:231:9|Unbound component ROM16X1A of instance LUT4_3 @W: Z198 :"C:\TFG\exp1\divfrec1.vhd":236:4:236:9|Unbound component ROM16X1A of instance LUT4_2 @W: Z198 :"C:\TFG\exp1\divfrec1.vhd":241:4:241:9|Unbound component ROM16X1A of instance LUT4_1 @W: Z198 :"C:\TFG\exp1\divfrec1.vhd":247:4:247:9|Unbound component ROM16X1A of instance LUT4_0 @W: Z198 :"C:\TFG\exp1\divfrec1.vhd":252:4:252:10|Unbound component MUX21 of instance muxb_20 @W: Z198 :"C:\TFG\exp1\divfrec1.vhd":256:4:256:10|Unbound component MUX21 of instance muxb_19 @W: Z198 :"C:\TFG\exp1\divfrec1.vhd":260:4:260:10|Unbound component MUX21 of instance muxb_18 @W: Z198 :"C:\TFG\exp1\divfrec1.vhd":264:4:264:10|Unbound component MUX21 of instance muxb_17 @W: Z198 :"C:\TFG\exp1\divfrec1.vhd":268:4:268:10|Unbound component MUX21 of instance muxb_16 @W: Z198 :"C:\TFG\exp1\divfrec1.vhd":272:4:272:10|Unbound component MUX21 of instance muxb_15 @W: Z198 :"C:\TFG\exp1\divfrec1.vhd":276:4:276:10|Unbound component MUX21 of instance muxb_14 @W: Z198 :"C:\TFG\exp1\divfrec1.vhd":280:4:280:10|Unbound component MUX21 of instance muxb_13 @W: Z198 :"C:\TFG\exp1\divfrec1.vhd":284:4:284:10|Unbound component MUX21 of instance muxb_12 @W: Z198 :"C:\TFG\exp1\divfrec1.vhd":288:4:288:10|Unbound component MUX21 of instance muxb_11 @W: Z198 :"C:\TFG\exp1\divfrec1.vhd":292:4:292:10|Unbound component MUX21 of instance muxb_10 @W: Z198 :"C:\TFG\exp1\divfrec1.vhd":296:4:296:9|Unbound component MUX21 of instance muxb_9 @W: Z198 :"C:\TFG\exp1\divfrec1.vhd":300:4:300:9|Unbound component MUX21 of instance muxb_8 @W: Z198 :"C:\TFG\exp1\divfrec1.vhd":304:4:304:9|Unbound component MUX21 of instance muxb_7 @W: Z198 :"C:\TFG\exp1\divfrec1.vhd":308:4:308:9|Unbound component MUX21 of instance muxb_6 @W: Z198 :"C:\TFG\exp1\divfrec1.vhd":312:4:312:9|Unbound component MUX21 of instance muxb_5 @W: Z198 :"C:\TFG\exp1\divfrec1.vhd":316:4:316:9|Unbound component MUX21 of instance muxb_4 @W: Z198 :"C:\TFG\exp1\divfrec1.vhd":320:4:320:9|Unbound component MUX21 of instance muxb_3 @W: Z198 :"C:\TFG\exp1\divfrec1.vhd":324:4:324:9|Unbound component MUX21 of instance muxb_2 @W: Z198 :"C:\TFG\exp1\divfrec1.vhd":328:4:328:9|Unbound component MUX21 of instance muxb_1 @W: Z198 :"C:\TFG\exp1\divfrec1.vhd":332:4:332:9|Unbound component MUX21 of instance muxb_0 @W: Z198 :"C:\TFG\exp1\divfrec1.vhd":336:4:336:8|Unbound component FD1P3DX of instance FF_20 @W: Z198 :"C:\TFG\exp1\divfrec1.vhd":340:4:340:8|Unbound component FD1P3DX of instance FF_19 @W: Z198 :"C:\TFG\exp1\divfrec1.vhd":344:4:344:8|Unbound component FD1P3DX of instance FF_18 @W: Z198 :"C:\TFG\exp1\divfrec1.vhd":348:4:348:8|Unbound component FD1P3DX of instance FF_17 @W: Z198 :"C:\TFG\exp1\divfrec1.vhd":352:4:352:8|Unbound component FD1P3DX of instance FF_16 @W: Z198 :"C:\TFG\exp1\divfrec1.vhd":356:4:356:8|Unbound component FD1P3DX of instance FF_15 @W: Z198 :"C:\TFG\exp1\divfrec1.vhd":360:4:360:8|Unbound component FD1P3DX of instance FF_14 @W: Z198 :"C:\TFG\exp1\divfrec1.vhd":364:4:364:8|Unbound component FD1P3DX of instance FF_13 @W: Z198 :"C:\TFG\exp1\divfrec1.vhd":368:4:368:8|Unbound component FD1P3DX of instance FF_12 @W: Z198 :"C:\TFG\exp1\divfrec1.vhd":372:4:372:8|Unbound component FD1P3DX of instance FF_11 @W: Z198 :"C:\TFG\exp1\divfrec1.vhd":376:4:376:8|Unbound component FD1P3DX of instance FF_10 @W: Z198 :"C:\TFG\exp1\divfrec1.vhd":380:4:380:7|Unbound component FD1P3DX of instance FF_9 @W: Z198 :"C:\TFG\exp1\divfrec1.vhd":384:4:384:7|Unbound component FD1P3DX of instance FF_8 @W: Z198 :"C:\TFG\exp1\divfrec1.vhd":388:4:388:7|Unbound component FD1P3DX of instance FF_7 @W: Z198 :"C:\TFG\exp1\divfrec1.vhd":392:4:392:7|Unbound component FD1P3DX of instance FF_6 @W: Z198 :"C:\TFG\exp1\divfrec1.vhd":396:4:396:7|Unbound component FD1P3DX of instance FF_5 @W: Z198 :"C:\TFG\exp1\divfrec1.vhd":400:4:400:7|Unbound component FD1P3DX of instance FF_4 @W: Z198 :"C:\TFG\exp1\divfrec1.vhd":404:4:404:7|Unbound component FD1P3DX of instance FF_3 @W: Z198 :"C:\TFG\exp1\divfrec1.vhd":408:4:408:7|Unbound component FD1P3DX of instance FF_2 @W: Z198 :"C:\TFG\exp1\divfrec1.vhd":412:4:412:7|Unbound component FD1P3DX of instance FF_1 @W: Z198 :"C:\TFG\exp1\divfrec1.vhd":416:4:416:7|Unbound component FD1P3DX of instance FF_0 @W: Z198 :"C:\TFG\exp1\divfrec1.vhd":423:4:423:10|Unbound component FADD2B of instance cnt_cia @W: Z198 :"C:\TFG\exp1\divfrec1.vhd":428:4:428:8|Unbound component CU2 of instance cnt_0 @W: Z198 :"C:\TFG\exp1\divfrec1.vhd":432:4:432:8|Unbound component CU2 of instance cnt_1 @W: Z198 :"C:\TFG\exp1\divfrec1.vhd":436:4:436:8|Unbound component CU2 of instance cnt_2 @W: Z198 :"C:\TFG\exp1\divfrec1.vhd":440:4:440:8|Unbound component CU2 of instance cnt_3 @W: Z198 :"C:\TFG\exp1\divfrec1.vhd":444:4:444:8|Unbound component CU2 of instance cnt_4 @W: Z198 :"C:\TFG\exp1\divfrec1.vhd":448:4:448:8|Unbound component CU2 of instance cnt_5 @W: Z198 :"C:\TFG\exp1\divfrec1.vhd":452:4:452:8|Unbound component CU2 of instance cnt_6 @W: Z198 :"C:\TFG\exp1\divfrec1.vhd":456:4:456:8|Unbound component CU2 of instance cnt_7 @W: Z198 :"C:\TFG\exp1\divfrec1.vhd":460:4:460:8|Unbound component CU2 of instance cnt_8 @W: Z198 :"C:\TFG\exp1\divfrec1.vhd":464:4:464:8|Unbound component CU2 of instance cnt_9 @W: Z198 :"C:\TFG\exp1\divfrec1.vhd":468:4:468:9|Unbound component CU2 of instance cnt_10 @W: Z198 :"C:\TFG\exp1\divfrec1.vhd":472:4:472:17|Unbound component VLO of instance scuba_vlo_inst @W: Z198 :"C:\TFG\exp1\cont_BCD.vhd":95:4:95:9|Unbound component ROM16X1A of instance LUT4_0 @W: Z198 :"C:\TFG\exp1\cont_BCD.vhd":100:4:100:9|Unbound component MUX21 of instance muxb_3 @W: Z198 :"C:\TFG\exp1\cont_BCD.vhd":104:4:104:9|Unbound component MUX21 of instance muxb_2 @W: Z198 :"C:\TFG\exp1\cont_BCD.vhd":108:4:108:9|Unbound component MUX21 of instance muxb_1 @W: Z198 :"C:\TFG\exp1\cont_BCD.vhd":112:4:112:9|Unbound component MUX21 of instance muxb_0 @W: Z198 :"C:\TFG\exp1\cont_BCD.vhd":116:4:116:7|Unbound component FD1P3DX of instance FF_3 @W: Z198 :"C:\TFG\exp1\cont_BCD.vhd":120:4:120:7|Unbound component FD1P3DX of instance FF_2 @W: Z198 :"C:\TFG\exp1\cont_BCD.vhd":124:4:124:7|Unbound component FD1P3DX of instance FF_1 @W: Z198 :"C:\TFG\exp1\cont_BCD.vhd":128:4:128:7|Unbound component FD1P3DX of instance FF_0 @W: Z198 :"C:\TFG\exp1\cont_BCD.vhd":132:4:132:17|Unbound component VLO of instance scuba_vlo_inst @W: Z198 :"C:\TFG\exp1\cont_BCD.vhd":138:4:138:10|Unbound component FADD2B of instance cnt_cia @W: Z198 :"C:\TFG\exp1\cont_BCD.vhd":143:4:143:8|Unbound component CU2 of instance cnt_0 @W: Z198 :"C:\TFG\exp1\cont_BCD.vhd":147:4:147:8|Unbound component CU2 of instance cnt_1 @W: Z198 :"C:\TFG\exp1\pll1.vhd":105:4:105:17|Unbound component VLO of instance scuba_vlo_inst @W: Z198 :"C:\TFG\exp1\pll1.vhd":108:4:108:12|Unbound component EHXPLLJ of instance PLLInst_0 @W: Z198 :"C:\TFG\exp1\cont_50mhz_1mhz.vhd":109:4:109:9|Unbound component ROM16X1A of instance LUT4_1 @W: Z198 :"C:\TFG\exp1\cont_50mhz_1mhz.vhd":114:4:114:9|Unbound component ROM16X1A of instance LUT4_0 @W: Z198 :"C:\TFG\exp1\cont_50mhz_1mhz.vhd":119:4:119:9|Unbound component MUX21 of instance muxb_5 @W: Z198 :"C:\TFG\exp1\cont_50mhz_1mhz.vhd":123:4:123:9|Unbound component MUX21 of instance muxb_4 @W: Z198 :"C:\TFG\exp1\cont_50mhz_1mhz.vhd":127:4:127:9|Unbound component MUX21 of instance muxb_3 @W: Z198 :"C:\TFG\exp1\cont_50mhz_1mhz.vhd":131:4:131:9|Unbound component MUX21 of instance muxb_2 @W: Z198 :"C:\TFG\exp1\cont_50mhz_1mhz.vhd":135:4:135:9|Unbound component MUX21 of instance muxb_1 @W: Z198 :"C:\TFG\exp1\cont_50mhz_1mhz.vhd":139:4:139:9|Unbound component MUX21 of instance muxb_0 @W: Z198 :"C:\TFG\exp1\cont_50mhz_1mhz.vhd":143:4:143:7|Unbound component FD1P3DX of instance FF_5 @W: Z198 :"C:\TFG\exp1\cont_50mhz_1mhz.vhd":147:4:147:7|Unbound component FD1P3DX of instance FF_4 @W: Z198 :"C:\TFG\exp1\cont_50mhz_1mhz.vhd":151:4:151:7|Unbound component FD1P3DX of instance FF_3 @W: Z198 :"C:\TFG\exp1\cont_50mhz_1mhz.vhd":155:4:155:7|Unbound component FD1P3DX of instance FF_2 @W: Z198 :"C:\TFG\exp1\cont_50mhz_1mhz.vhd":159:4:159:7|Unbound component FD1P3DX of instance FF_1 @W: Z198 :"C:\TFG\exp1\cont_50mhz_1mhz.vhd":163:4:163:7|Unbound component FD1P3DX of instance FF_0 @W: Z198 :"C:\TFG\exp1\cont_50mhz_1mhz.vhd":167:4:167:17|Unbound component VLO of instance scuba_vlo_inst @W: Z198 :"C:\TFG\exp1\cont_50mhz_1mhz.vhd":173:4:173:10|Unbound component FADD2B of instance cnt_cia @W: Z198 :"C:\TFG\exp1\cont_50mhz_1mhz.vhd":178:4:178:8|Unbound component CU2 of instance cnt_0 @W: Z198 :"C:\TFG\exp1\cont_50mhz_1mhz.vhd":182:4:182:8|Unbound component CU2 of instance cnt_1 @W: Z198 :"C:\TFG\exp1\cont_50mhz_1mhz.vhd":186:4:186:8|Unbound component CU2 of instance cnt_2 ======================================================================================= For a summary of linker messages for components that did not bind, please see log file: @L: C:\TFG\exp1\proyecto_global\synwork\proyecto_global_proyecto_global_comp.linkerlog ======================================================================================= At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Thu Sep 21 05:01:54 2017 ###########################################################] @END At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Thu Sep 21 05:01:54 2017 ###########################################################] Synopsys Netlist Linker, version comp2016q2rc, Build 192R, built Jul 5 2016 @N|Running in 64-bit mode File C:\TFG\exp1\proyecto_global\synwork\proyecto_global_proyecto_global_comp.srs changed - recompiling At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Thu Sep 21 05:01:56 2017 ###########################################################] Pre-mapping Report Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1498R, Built Jul 5 2016 10:30:31 Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Product Version L-2016.03L-1 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB) @A: MF827 |No constraint file specified. @L: C:\TFG\exp1\proyecto_global\proyecto_global_proyecto_global_scck.rpt Printing clock summary report in "C:\TFG\exp1\proyecto_global\proyecto_global_proyecto_global_scck.rpt" file @N: MF248 |Running in 64-bit mode. @N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 112MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 114MB) ICG Latch Removal Summary: Number of ICG latches removed: 0 Number of ICG latches not removed: 0 syn_allowed_resources : blockrams=7 set on top level netlist esquema_global Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB) Clock Summary ***************** Start Requested Requested Clock Clock Clock Clock Frequency Period Type Group Load ------------------------------------------------------------------------------------------------------------- System 1.0 MHz 1000.000 system system_clkgroup 0 esquema_global|N_25_inferred_clock 2.1 MHz 480.769 inferred Inferred_clkgroup_2 21 esquema_global|N_28_inferred_clock 1.0 MHz 1000.000 inferred Inferred_clkgroup_3 21 esquema_global|clk_ext_sal 1.0 MHz 1000.000 inferred Inferred_clkgroup_0 6 pll1|CLKOS3_inferred_clock 1.0 MHz 1000.000 inferred Inferred_clkgroup_1 12 ============================================================================================================= @W: MT529 :"c:\tfg\exp1\cont_50mhz_1mhz.vhd":143:4:143:7|Found inferred clock esquema_global|clk_ext_sal which controls 6 sequential elements including I52.FF_5. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. @W: MT529 :"c:\tfg\exp1\cont_bcd.vhd":116:4:116:7|Found inferred clock pll1|CLKOS3_inferred_clock which controls 12 sequential elements including I8.FF_3. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. @W: MT529 :"c:\tfg\exp1\divfrec1.vhd":336:4:336:8|Found inferred clock esquema_global|N_25_inferred_clock which controls 21 sequential elements including I7.FF_20. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. @W: MT529 :"c:\tfg\exp1\control_disp.vhd":22:8:22:9|Found inferred clock esquema_global|N_28_inferred_clock which controls 21 sequential elements including I69.cnt[20:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. Finished Pre Mapping Phase. Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB) None None Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB) Pre-mapping successful! At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 141MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Thu Sep 21 05:01:56 2017 ###########################################################] Map & Optimize Report Synopsys Lattice Technology Mapper, Version maplat, Build 1498R, Built Jul 5 2016 10:30:31 Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Product Version L-2016.03L-1 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) @N: MF248 |Running in 64-bit mode. @N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 111MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 114MB) Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB) Available hyper_sources - for debug and ip models None Found @W: FA239 :"c:\tfg\exp1\decodif.vhd":25:1:25:9|ROM I23.SEGMENTOS_1[6:0] (in view: work.esquema_global(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance. @W: FA239 :"c:\tfg\exp1\decodif.vhd":25:1:25:9|ROM I35.SEGMENTOS_1[6:0] (in view: work.esquema_global(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance. @W: FA239 :"c:\tfg\exp1\decodif.vhd":25:1:25:9|ROM I23.SEGMENTOS_1[6:0] (in view: work.esquema_global(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance. @N: MO106 :"c:\tfg\exp1\decodif.vhd":25:1:25:9|Found ROM .delname. (in view: work.esquema_global(verilog)) with 10 words by 7 bits. @W: FA239 :"c:\tfg\exp1\decodif.vhd":25:1:25:9|ROM I35.SEGMENTOS_1[6:0] (in view: work.esquema_global(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance. @N: MO106 :"c:\tfg\exp1\decodif.vhd":25:1:25:9|Found ROM .delname. (in view: work.esquema_global(verilog)) with 10 words by 7 bits. Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 141MB) Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 141MB) Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 141MB) Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 141MB) Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 141MB) Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 141MB) Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 141MB) Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 141MB) Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 141MB) Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 141MB) Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:00s 475.80ns 36 / 21 Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 141MB) @N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 141MB) @S |Clock Optimization Summary #### START OF CLOCK OPTIMIZATION REPORT #####[ 1 non-gated/non-generated clock tree(s) driving 6 clock pin(s) of sequential element(s) 3 gated/generated clock tree(s) driving 54 clock pin(s) of sequential element(s) 0 instances converted, 54 sequential instances remain driven by gated/generated clocks =========================== Non-Gated/Non-Generated Clocks ============================ Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance --------------------------------------------------------------------------------------- @K:CKID0004 clk_ext_sal port 6 I52.FF_0 ======================================================================================= ================================================================ Gated/Generated Clocks ================================================================= Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance Explanation --------------------------------------------------------------------------------------------------------------------------------------------------------- @K:CKID0001 I5 OSCH 21 I7.FF_0 No gated clock conversion method for cell cell:LUCENT.FD1P3DX @K:CKID0002 I53.PLLInst_0 EHXPLLJ 12 I43.FF_0 No gated clock conversion method for cell cell:LUCENT.FD1P3DX @K:CKID0003 I71 AND2 21 I69.cnt[20] No gated clock conversion method for cell cell:LUCENT.FD1S3DX ========================================================================================================================================================= ##### END OF CLOCK OPTIMIZATION REPORT ######] Start Writing Netlists (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 108MB peak: 141MB) Writing Analyst data base C:\TFG\exp1\proyecto_global\synwork\proyecto_global_proyecto_global_m.srm Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 139MB peak: 141MB) Writing EDIF Netlist and constraint files @N: FX1056 |Writing EDF file: C:\TFG\exp1\proyecto_global\proyecto_global_proyecto_global.edi L-2016.03L-1 @N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 145MB) Start final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 145MB) @W: MT246 :"c:\tfg\exp1\proyecto_global\esquema_global.v":85:5:85:7|Blackbox AND4 is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W: MT246 :"c:\tfg\exp1\proyecto_global\esquema_global.v":68:5:68:7|Blackbox AND3 is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W: MT246 :"c:\tfg\exp1\pll1.vhd":108:4:108:12|Blackbox EHXPLLJ is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W: MT420 |Found inferred clock esquema_global|clk_ext_sal with period 1000.00ns. Please declare a user-defined clock on object "p:clk_ext_sal" @W: MT420 |Found inferred clock esquema_global|N_28_inferred_clock with period 1000.00ns. Please declare a user-defined clock on object "n:N_28" @W: MT420 |Found inferred clock esquema_global|N_25_inferred_clock with period 480.77ns. Please declare a user-defined clock on object "n:N_25" @W: MT420 |Found inferred clock pll1|CLKOS3_inferred_clock with period 1000.00ns. Please declare a user-defined clock on object "n:I53.CLKOS3" ##### START OF TIMING REPORT #####[ # Timing Report written on Thu Sep 21 05:01:58 2017 # Top view: esquema_global Requested Frequency: 1.0 MHz Wire load mode: top Paths requested: 5 Constraint File(s): @N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing. @N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock. Performance Summary ******************* Worst slack in design: 475.795 @N: MT286 |System clock period 0.000 stretches to negative invalid value -- ignoring stretching. Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group ------------------------------------------------------------------------------------------------------------------------------------------- esquema_global|N_25_inferred_clock 2.1 MHz 201.0 MHz 480.769 4.974 475.795 inferred Inferred_clkgroup_2 esquema_global|N_28_inferred_clock 1.0 MHz 165.2 MHz 1000.000 6.055 993.946 inferred Inferred_clkgroup_3 esquema_global|clk_ext_sal 1.0 MHz 254.8 MHz 1000.000 3.925 996.075 inferred Inferred_clkgroup_0 pll1|CLKOS3_inferred_clock 1.0 MHz 334.2 MHz 1000.000 2.993 997.007 inferred Inferred_clkgroup_1 System 1.0 MHz 1.9 MHz 1000.000 519.336 480.664 system system_clkgroup =========================================================================================================================================== Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise ----------------------------------------------------------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ----------------------------------------------------------------------------------------------------------------------------------------------------------------- System System | 1000.000 1000.000 | No paths - | No paths - | No paths - System esquema_global|clk_ext_sal | 1000.000 999.894 | No paths - | No paths - | No paths - System pll1|CLKOS3_inferred_clock | 1000.000 999.528 | No paths - | No paths - | No paths - System esquema_global|N_25_inferred_clock | 480.769 480.664 | No paths - | No paths - | No paths - esquema_global|clk_ext_sal System | 1000.000 996.075 | No paths - | No paths - | No paths - pll1|CLKOS3_inferred_clock System | 1000.000 997.007 | No paths - | No paths - | No paths - esquema_global|N_25_inferred_clock System | 480.769 475.795 | No paths - | No paths - | No paths - esquema_global|N_28_inferred_clock esquema_global|N_28_inferred_clock | 1000.000 993.946 | No paths - | No paths - | No paths - ================================================================================================================================================================= Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: esquema_global|N_25_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------- I7.FF_6 esquema_global|N_25_inferred_clock FD1P3DX Q Q[14] 1.044 475.795 I7.FF_11 esquema_global|N_25_inferred_clock FD1P3DX Q Q[9] 1.044 475.795 I7.FF_13 esquema_global|N_25_inferred_clock FD1P3DX Q Q[7] 1.044 475.795 I7.FF_14 esquema_global|N_25_inferred_clock FD1P3DX Q Q[6] 1.044 475.795 I7.FF_15 esquema_global|N_25_inferred_clock FD1P3DX Q Q[5] 1.044 475.795 I7.FF_16 esquema_global|N_25_inferred_clock FD1P3DX Q Q[4] 1.044 475.795 I7.FF_17 esquema_global|N_25_inferred_clock FD1P3DX Q Q[3] 1.044 475.795 I7.FF_18 esquema_global|N_25_inferred_clock FD1P3DX Q Q[2] 1.044 475.795 I7.FF_19 esquema_global|N_25_inferred_clock FD1P3DX Q Q[1] 1.044 475.795 I7.FF_20 esquema_global|N_25_inferred_clock FD1P3DX Q Q[0] 1.044 475.795 ===================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------- I7.muxb_0 esquema_global|N_25_inferred_clock MUX21 SD dec0_sr1fbd00 480.769 475.795 I7.muxb_1 esquema_global|N_25_inferred_clock MUX21 SD dec0_sr1fbd00 480.769 475.795 I7.muxb_2 esquema_global|N_25_inferred_clock MUX21 SD dec0_sr1fbd00 480.769 475.795 I7.muxb_3 esquema_global|N_25_inferred_clock MUX21 SD dec0_sr1fbd00 480.769 475.795 I7.muxb_4 esquema_global|N_25_inferred_clock MUX21 SD dec0_sr1fbd00 480.769 475.795 I7.muxb_5 esquema_global|N_25_inferred_clock MUX21 SD dec0_sr1fbd00 480.769 475.795 I7.muxb_6 esquema_global|N_25_inferred_clock MUX21 SD dec0_sr1fbd00 480.769 475.795 I7.muxb_7 esquema_global|N_25_inferred_clock MUX21 SD dec0_sr1fbd00 480.769 475.795 I7.muxb_8 esquema_global|N_25_inferred_clock MUX21 SD dec0_sr1fbd00 480.769 475.795 I7.muxb_9 esquema_global|N_25_inferred_clock MUX21 SD dec0_sr1fbd00 480.769 475.795 ============================================================================================================= Worst Path Information *********************** Path information for path number 1: Requested Period: 480.769 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) + Estimated clock delay at ending point: 0.000 = Required time: 480.769 - Propagation time: 4.974 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : 475.795 Number of logic level(s): 4 Starting point: I7.FF_6 / Q Ending point: I7.muxb_0 / SD The start point is clocked by esquema_global|N_25_inferred_clock [rising] on pin CK The end point is clocked by System [rising] Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------- I7.FF_6 FD1P3DX Q Out 1.044 1.044 - Q[14] Net - - - - 2 I7.INV_0 INV A In 0.000 1.044 - I7.INV_0 INV Z Out 0.568 1.612 - tdataout14_inv Net - - - - 1 I7.LUT4_4 ROM16X1A AD1 In 0.000 1.612 - I7.LUT4_4 ROM16X1A DO0 Out 1.017 2.629 - func_and_inet_3 Net - - - - 1 I7.LUT4_1 ROM16X1A AD0 In 0.000 2.629 - I7.LUT4_1 ROM16X1A DO0 Out 1.017 3.645 - func_and_inet_6 Net - - - - 1 I7.LUT4_0 ROM16X1A AD3 In 0.000 3.645 - I7.LUT4_0 ROM16X1A DO0 Out 1.329 4.974 - dec0_sr1fbd00 Net - - - - 21 I7.muxb_0 MUX21 SD In 0.000 4.974 - ================================================================================== ==================================== Detailed Report for Clock: esquema_global|N_28_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------- I69.cnt[0] esquema_global|N_28_inferred_clock FD1S3DX Q cnt[0] 1.148 993.946 I69.cnt[1] esquema_global|N_28_inferred_clock FD1S3DX Q cnt[1] 1.236 994.000 I69.cnt[2] esquema_global|N_28_inferred_clock FD1S3DX Q cnt[2] 1.044 994.192 I69.cnt[3] esquema_global|N_28_inferred_clock FD1S3DX Q cnt[3] 1.044 994.335 I69.cnt[4] esquema_global|N_28_inferred_clock FD1S3DX Q cnt[4] 1.044 994.335 I69.cnt[5] esquema_global|N_28_inferred_clock FD1S3DX Q cnt[5] 1.148 994.374 I69.cnt[6] esquema_global|N_28_inferred_clock FD1S3DX Q cnt[6] 1.148 994.374 I69.cnt[7] esquema_global|N_28_inferred_clock FD1S3DX Q cnt[7] 1.044 994.621 I69.cnt[8] esquema_global|N_28_inferred_clock FD1S3DX Q cnt[8] 1.044 994.621 I69.cnt[9] esquema_global|N_28_inferred_clock FD1S3DX Q cnt[9] 1.148 994.659 ======================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------- I69.cnt[19] esquema_global|N_28_inferred_clock FD1S3DX D cnt_3[19] 1000.089 993.946 I69.cnt[17] esquema_global|N_28_inferred_clock FD1S3DX D cnt_3[17] 1000.089 994.088 I69.cnt[18] esquema_global|N_28_inferred_clock FD1S3DX D cnt_3[18] 1000.089 994.088 I69.cnt[16] esquema_global|N_28_inferred_clock FD1S3DX D cnt_3[16] 1000.089 994.231 I69.cnt[20] esquema_global|N_28_inferred_clock FD1S3DX D un2_cnt_1[20] 999.894 994.368 I69.cnt[14] esquema_global|N_28_inferred_clock FD1S3DX D cnt_3[14] 1000.089 994.374 I69.cnt[15] esquema_global|N_28_inferred_clock FD1S3DX D un2_cnt_1[15] 999.894 994.654 I69.cnt[9] esquema_global|N_28_inferred_clock FD1S3DX D cnt_3[9] 1000.089 994.659 I69.cnt[13] esquema_global|N_28_inferred_clock FD1S3DX D un2_cnt_1[13] 999.894 994.796 I69.cnt[11] esquema_global|N_28_inferred_clock FD1S3DX D un2_cnt_1[11] 999.894 994.939 ================================================================================================================= Worst Path Information *********************** Path information for path number 1: Requested Period: 1000.000 - Setup time: -0.089 + Clock delay at ending point: 0.000 (ideal) = Required time: 1000.089 - Propagation time: 6.143 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 993.946 Number of logic level(s): 12 Starting point: I69.cnt[0] / Q Ending point: I69.cnt[19] / D The start point is clocked by esquema_global|N_28_inferred_clock [rising] on pin CK The end point is clocked by esquema_global|N_28_inferred_clock [rising] on pin CK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------- I69.cnt[0] FD1S3DX Q Out 1.148 1.148 - cnt[0] Net - - - - 4 I69.un2_cnt_1_cry_0_0 CCU2D A1 In 0.000 1.148 - I69.un2_cnt_1_cry_0_0 CCU2D COUT Out 1.545 2.692 - un2_cnt_1_cry_0 Net - - - - 1 I69.un2_cnt_1_cry_1_0 CCU2D CIN In 0.000 2.692 - I69.un2_cnt_1_cry_1_0 CCU2D COUT Out 0.143 2.835 - un2_cnt_1_cry_2 Net - - - - 1 I69.un2_cnt_1_cry_3_0 CCU2D CIN In 0.000 2.835 - I69.un2_cnt_1_cry_3_0 CCU2D COUT Out 0.143 2.978 - un2_cnt_1_cry_4 Net - - - - 1 I69.un2_cnt_1_cry_5_0 CCU2D CIN In 0.000 2.978 - I69.un2_cnt_1_cry_5_0 CCU2D COUT Out 0.143 3.121 - un2_cnt_1_cry_6 Net - - - - 1 I69.un2_cnt_1_cry_7_0 CCU2D CIN In 0.000 3.121 - I69.un2_cnt_1_cry_7_0 CCU2D COUT Out 0.143 3.264 - un2_cnt_1_cry_8 Net - - - - 1 I69.un2_cnt_1_cry_9_0 CCU2D CIN In 0.000 3.264 - I69.un2_cnt_1_cry_9_0 CCU2D COUT Out 0.143 3.406 - un2_cnt_1_cry_10 Net - - - - 1 I69.un2_cnt_1_cry_11_0 CCU2D CIN In 0.000 3.406 - I69.un2_cnt_1_cry_11_0 CCU2D COUT Out 0.143 3.549 - un2_cnt_1_cry_12 Net - - - - 1 I69.un2_cnt_1_cry_13_0 CCU2D CIN In 0.000 3.549 - I69.un2_cnt_1_cry_13_0 CCU2D COUT Out 0.143 3.692 - un2_cnt_1_cry_14 Net - - - - 1 I69.un2_cnt_1_cry_15_0 CCU2D CIN In 0.000 3.692 - I69.un2_cnt_1_cry_15_0 CCU2D COUT Out 0.143 3.835 - un2_cnt_1_cry_16 Net - - - - 1 I69.un2_cnt_1_cry_17_0 CCU2D CIN In 0.000 3.835 - I69.un2_cnt_1_cry_17_0 CCU2D COUT Out 0.143 3.978 - un2_cnt_1_cry_18 Net - - - - 1 I69.un2_cnt_1_cry_19_0 CCU2D CIN In 0.000 3.978 - I69.un2_cnt_1_cry_19_0 CCU2D S0 Out 1.549 5.527 - un2_cnt_1_cry_19_0_S0 Net - - - - 1 I69.cnt_3[19] ORCALUT4 D In 0.000 5.527 - I69.cnt_3[19] ORCALUT4 Z Out 0.617 6.143 - cnt_3[19] Net - - - - 1 I69.cnt[19] FD1S3DX D In 0.000 6.143 - ========================================================================================= ==================================== Detailed Report for Clock: esquema_global|clk_ext_sal ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------- I52.FF_2 esquema_global|clk_ext_sal FD1P3DX Q S1MZ[3] 1.108 996.075 I52.FF_3 esquema_global|clk_ext_sal FD1P3DX Q S1MZ[2] 1.108 996.075 I52.FF_5 esquema_global|clk_ext_sal FD1P3DX Q S1MZ[0] 1.108 996.075 I52.FF_4 esquema_global|clk_ext_sal FD1P3DX Q S1MZ[1] 1.108 996.643 I52.FF_0 esquema_global|clk_ext_sal FD1P3DX Q S1MZ[5] 1.108 997.659 I52.FF_1 esquema_global|clk_ext_sal FD1P3DX Q S1MZ[4] 1.108 997.659 =============================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------- I52.muxb_0 esquema_global|clk_ext_sal MUX21 SD dec0_sr32 1000.000 996.075 I52.muxb_1 esquema_global|clk_ext_sal MUX21 SD dec0_sr32 1000.000 996.075 I52.muxb_2 esquema_global|clk_ext_sal MUX21 SD dec0_sr32 1000.000 996.075 I52.muxb_3 esquema_global|clk_ext_sal MUX21 SD dec0_sr32 1000.000 996.075 I52.muxb_4 esquema_global|clk_ext_sal MUX21 SD dec0_sr32 1000.000 996.075 I52.muxb_5 esquema_global|clk_ext_sal MUX21 SD dec0_sr32 1000.000 996.075 I70 esquema_global|clk_ext_sal AND3 A N_33 1000.000 998.324 I70 esquema_global|clk_ext_sal AND3 B N_31 1000.000 998.324 I70 esquema_global|clk_ext_sal AND3 C N_32 1000.000 998.324 I51 esquema_global|clk_ext_sal AND3 A S1MZ[5] 1000.000 998.892 ================================================================================================== Worst Path Information *********************** Path information for path number 1: Requested Period: 1000.000 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) + Estimated clock delay at ending point: 0.000 = Required time: 1000.000 - Propagation time: 3.925 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 996.075 Number of logic level(s): 3 Starting point: I52.FF_2 / Q Ending point: I52.muxb_0 / SD The start point is clocked by esquema_global|clk_ext_sal [rising] on pin CK The end point is clocked by System [rising] Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------- I52.FF_2 FD1P3DX Q Out 1.108 1.108 - S1MZ[3] Net - - - - 3 I52.INV_0 INV A In 0.000 1.108 - I52.INV_0 INV Z Out 0.568 1.676 - tdataout3_inv Net - - - - 1 I52.LUT4_1 ROM16X1A AD0 In 0.000 1.676 - I52.LUT4_1 ROM16X1A DO0 Out 1.017 2.693 - func_and_inet Net - - - - 1 I52.LUT4_0 ROM16X1A AD3 In 0.000 2.693 - I52.LUT4_0 ROM16X1A DO0 Out 1.233 3.925 - dec0_sr32 Net - - - - 6 I52.muxb_0 MUX21 SD In 0.000 3.925 - ================================================================================= ==================================== Detailed Report for Clock: pll1|CLKOS3_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------- I8.FF_1 pll1|CLKOS3_inferred_clock FD1P3DX Q SL[2] 1.232 997.007 I8.FF_2 pll1|CLKOS3_inferred_clock FD1P3DX Q SL[1] 1.232 997.007 I27.FF_1 pll1|CLKOS3_inferred_clock FD1P3DX Q R[2] 1.228 997.011 I27.FF_2 pll1|CLKOS3_inferred_clock FD1P3DX Q R[1] 1.228 997.011 I43.FF_1 pll1|CLKOS3_inferred_clock FD1P3DX Q ST[2] 1.148 997.091 I43.FF_2 pll1|CLKOS3_inferred_clock FD1P3DX Q ST[1] 1.148 997.091 I8.FF_0 pll1|CLKOS3_inferred_clock FD1P3DX Q SL[3] 1.232 997.575 I8.FF_3 pll1|CLKOS3_inferred_clock FD1P3DX Q SL[0] 1.232 997.575 I27.FF_0 pll1|CLKOS3_inferred_clock FD1P3DX Q R[3] 1.228 997.579 I27.FF_3 pll1|CLKOS3_inferred_clock FD1P3DX Q R[0] 1.228 997.579 ============================================================================================= Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------- I8.muxb_0 pll1|CLKOS3_inferred_clock MUX21 SD dec0_sr9 1000.000 997.007 I8.muxb_1 pll1|CLKOS3_inferred_clock MUX21 SD dec0_sr9 1000.000 997.007 I8.muxb_2 pll1|CLKOS3_inferred_clock MUX21 SD dec0_sr9 1000.000 997.007 I8.muxb_3 pll1|CLKOS3_inferred_clock MUX21 SD dec0_sr9 1000.000 997.007 I27.muxb_0 pll1|CLKOS3_inferred_clock MUX21 SD dec0_sr9 1000.000 997.011 I27.muxb_1 pll1|CLKOS3_inferred_clock MUX21 SD dec0_sr9 1000.000 997.011 I27.muxb_2 pll1|CLKOS3_inferred_clock MUX21 SD dec0_sr9 1000.000 997.011 I27.muxb_3 pll1|CLKOS3_inferred_clock MUX21 SD dec0_sr9 1000.000 997.011 I43.muxb_0 pll1|CLKOS3_inferred_clock MUX21 SD dec0_sr9 1000.000 997.091 I43.muxb_1 pll1|CLKOS3_inferred_clock MUX21 SD dec0_sr9 1000.000 997.091 ================================================================================================= Worst Path Information *********************** Path information for path number 1: Requested Period: 1000.000 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) + Estimated clock delay at ending point: 0.000 = Required time: 1000.000 - Propagation time: 2.993 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 997.007 Number of logic level(s): 2 Starting point: I8.FF_1 / Q Ending point: I8.muxb_0 / SD The start point is clocked by pll1|CLKOS3_inferred_clock [rising] on pin CK The end point is clocked by System [rising] Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------- I8.FF_1 FD1P3DX Q Out 1.232 1.232 - SL[2] Net - - - - 10 I8.INV_0 INV A In 0.000 1.232 - I8.INV_0 INV Z Out 0.568 1.800 - tdataout2_inv Net - - - - 1 I8.LUT4_0 ROM16X1A AD1 In 0.000 1.800 - I8.LUT4_0 ROM16X1A DO0 Out 1.193 2.993 - dec0_sr9 Net - - - - 4 I8.muxb_0 MUX21 SD In 0.000 2.993 - ================================================================================= ==================================== Detailed Report for Clock: System ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------- I7.muxb_0 System MUX21 Z ldataout20 0.000 480.664 I7.muxb_1 System MUX21 Z ldataout19 0.000 480.664 I7.muxb_2 System MUX21 Z ldataout18 0.000 480.664 I7.muxb_3 System MUX21 Z ldataout17 0.000 480.664 I7.muxb_4 System MUX21 Z ldataout16 0.000 480.664 I7.muxb_5 System MUX21 Z ldataout15 0.000 480.664 I7.muxb_6 System MUX21 Z ldataout14 0.000 480.664 I7.muxb_7 System MUX21 Z ldataout13 0.000 480.664 I7.muxb_8 System MUX21 Z ldataout12 0.000 480.664 I7.muxb_9 System MUX21 Z ldataout11 0.000 480.664 ================================================================================ Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ---------------------------------------------------------------------------------- I7.FF_0 System FD1P3DX D ldataout20 480.664 480.664 I7.FF_1 System FD1P3DX D ldataout19 480.664 480.664 I7.FF_2 System FD1P3DX D ldataout18 480.664 480.664 I7.FF_3 System FD1P3DX D ldataout17 480.664 480.664 I7.FF_4 System FD1P3DX D ldataout16 480.664 480.664 I7.FF_5 System FD1P3DX D ldataout15 480.664 480.664 I7.FF_6 System FD1P3DX D ldataout14 480.664 480.664 I7.FF_7 System FD1P3DX D ldataout13 480.664 480.664 I7.FF_8 System FD1P3DX D ldataout12 480.664 480.664 I7.FF_9 System FD1P3DX D ldataout11 480.664 480.664 ================================================================================== Worst Path Information *********************** Path information for path number 1: Requested Period: 480.769 - Setup time: 0.106 + Clock delay at ending point: 0.000 (ideal) = Required time: 480.664 - Propagation time: 0.000 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : 480.664 Number of logic level(s): 0 Starting point: I7.muxb_0 / Z Ending point: I7.FF_0 / D The start point is clocked by System [rising] The end point is clocked by esquema_global|N_25_inferred_clock [rising] on pin CK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------- I7.muxb_0 MUX21 Z Out 0.000 0.000 - ldataout20 Net - - - - 1 I7.FF_0 FD1P3DX D In 0.000 0.000 - ================================================================================ ##### END OF TIMING REPORT #####] Constraints that could not be applied None Finished final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 145MB) Finished timing report (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 145MB) --------------------------------------- Resource Usage Report Part: lcmxo2_1200ze-1 Register bits: 60 of 1280 (5%) PIC Latch: 0 I/O cells: 25 Details: AND2: 2 AND3: 2 AND4: 2 CCU2D: 11 CU2: 20 FADD2B: 5 FD1P3DX: 39 FD1S3DX: 21 GSR: 1 IB: 4 INV: 30 MUX21: 39 OB: 21 ORCALUT4: 36 OSCH: 1 PUR: 1 ROM16X1A: 13 VHI: 7 VLO: 8 false: 2 true: 3 Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 31MB peak: 145MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Thu Sep 21 05:01:59 2017 ###########################################################]