Lattice Mapping Report File for Design Module 'esquema_global' Design Information Command line: map -a MachXO2 -p LCMXO2-1200ZE -t TQFP144 -s 1 -oc Commercial proyecto_global_proyecto_global.ngd -o proyecto_global_proyecto_global_map.ncd -pr proyecto_global_proyecto_global.prf -mp proyecto_global_proyecto_global.mrp -lpf C:/TFG/exp1_meg/proyecto_global/proyecto_global_proyecto_global_synpli fy.lpf -lpf C:/TFG/exp1_meg/proyecto_global.lpf -c 0 -gui -msgset C:/TFG/exp1_meg/promote.xml Target Vendor: LATTICE Target Device: LCMXO2-1200ZETQFP144 Target Performance: 1 Mapper: xo2c00, version: Diamond Version 3.8.0.115.3 Mapped on: 09/27/17 05:40:57 Design Summary Number of registers: 72 out of 1604 (4%) PFU registers: 72 out of 1280 (6%) PIO registers: 0 out of 324 (0%) Number of SLICEs: 88 out of 640 (14%) SLICEs as Logic/ROM: 88 out of 640 (14%) SLICEs as RAM: 0 out of 480 (0%) SLICEs as Carry: 36 out of 640 (6%) Number of LUT4s: 176 out of 1280 (14%) Number used as logic LUTs: 104 Number used as distributed RAM: 0 Number used as ripple logic: 72 Number used as shift registers: 0 Number of PIO sites used: 25 + 4(JTAG) out of 108 (27%) Number of block RAMs: 0 out of 7 (0%) Number of GSRs: 1 out of 1 (100%) EFB used : No JTAG used : No Readback used : No Oscillator used : Yes Startup used : No POR : On Bandgap : On Number of Power Controller: 0 out of 1 (0%) Number of Dynamic Bank Controller (BCINRD): 0 out of 4 (0%) Number of Dynamic Bank Controller (BCLVDSO): 0 out of 1 (0%) Number of DCCA: 0 out of 8 (0%) Number of DCMA: 0 out of 2 (0%) Number of PLLs: 1 out of 1 (100%) Number of DQSDLLs: 0 out of 2 (0%) Number of CLKDIVC: 0 out of 4 (0%) Number of ECLKSYNCA: 0 out of 4 (0%) Number of ECLKBRIDGECS: 0 out of 2 (0%) Notes:- 1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of distributed RAMs) + 2*(Number of ripple logic) 2. Number of logic LUT4s does not include count of distributed RAM and ripple logic. Number of clocks: 5 Net N_25: 11 loads, 11 rising, 0 falling (Driver: I5 ) Net N_27: 6 loads, 6 rising, 0 falling (Driver: I53/PLLInst_0 ) Net Q[20]: 6 loads, 6 rising, 0 falling (Driver: I7/FF_0 ) Net N_38: 12 loads, 12 rising, 0 falling (Driver: I83 ) Net clk_ext_sal_c: 4 loads, 4 rising, 0 falling (Driver: PIO clk_ext_sal ) Number of Clock Enables: 3 Net N_36: 2 loads, 2 LSLICEs Net cont_BCD_3dig_c: 2 loads, 2 LSLICEs Net N_14: 2 loads, 2 LSLICEs Number of local set/reset loads for net Q[20] merged into GSR: 21 Number of LSRs: 2 Net N_22: 11 loads, 11 LSLICEs Net s2: 6 loads, 6 LSLICEs Number of nets driven by tri-state buffers: 0 Top 10 highest fanout non-clock nets: Net I7/func_and_inet_4: 21 loads Net I7/func_and_inet_6: 21 loads Net I69/cnt[1]: 17 loads Net I69/un3_sal2_0_o2: 16 loads Net I69/cnt7_i_i_a3_13: 14 loads Net N_22: 11 loads Net S1MZ[4]: 8 loads Net S1MZ[5]: 8 loads Net R[0]: 7 loads Net SLU[0]: 7 loads Number of warnings: 1 Number of errors: 0 Design Errors/Warnings WARNING - map: Using local reset signal 'Q[20]' to infer global GSR net. IO (PIO) Attributes +---------------------+-----------+-----------+------------+ | IO Name | Direction | Levelmode | IO | | | | IO_TYPE | Register | +---------------------+-----------+-----------+------------+ | sal1hz | OUTPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ | aclr_a1hz | INPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ | Rx | OUTPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ | cont_BCD_3dig | INPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ | clk_ext_sal | INPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ | clk_ext_en | OUTPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ | s_led0 | OUTPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ | s_led1 | OUTPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ | s_led2 | OUTPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ | s_led3 | OUTPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ | seg_g | OUTPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ | seg_a | OUTPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ | seg_d | OUTPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ | seg_c | OUTPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ | seg_b | OUTPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ | seg_f | OUTPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ | seg_e | OUTPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ | dseg_a | OUTPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ | dseg_b | OUTPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ | dseg_c | OUTPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ | dseg_d | OUTPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ | dseg_e | OUTPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ | dseg_f | OUTPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ | dseg_g | OUTPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ | in_osch | INPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ Removed logic Block GND undriven or does not drive anything - clipped. Signal N_8 was merged into signal SL[1] Signal N_15 was merged into signal ST[1] Signal N_16 was merged into signal ST[2] Signal N_41 was merged into signal S1MZ[3] Signal N_40 was merged into signal S1MZ[2] Signal N_37 was merged into signal S1MZ[0] Signal N_9 was merged into signal SL[2] Signal I7/func_and_inet_5 was merged into signal Q[20] Signal I7/GND undriven or does not drive anything - clipped. Signal I7/VCC undriven or does not drive anything - clipped. Signal I8/VCC undriven or does not drive anything - clipped. Signal I8/GND undriven or does not drive anything - clipped. Signal I43/VCC undriven or does not drive anything - clipped. Signal I43/GND undriven or does not drive anything - clipped. Signal I27/VCC undriven or does not drive anything - clipped. Signal I27/GND undriven or does not drive anything - clipped. Signal I53/GND undriven or does not drive anything - clipped. Signal I52/GND undriven or does not drive anything - clipped. Signal I52/VCC undriven or does not drive anything - clipped. Signal I69/GND undriven or does not drive anything - clipped. Signal I7/cnt_cia_S1 undriven or does not drive anything - clipped. Signal I7/cnt_cia_S0 undriven or does not drive anything - clipped. Signal I7/cnt_10_NC1 undriven or does not drive anything - clipped. Signal I7/co10 undriven or does not drive anything - clipped. Signal I8/co1 undriven or does not drive anything - clipped. Signal I8/cnt_cia_S1_0 undriven or does not drive anything - clipped. Signal I8/cnt_cia_S0_0 undriven or does not drive anything - clipped. Signal I43/co1 undriven or does not drive anything - clipped. Signal I43/cnt_cia_S1_1 undriven or does not drive anything - clipped. Signal I43/cnt_cia_S0_1 undriven or does not drive anything - clipped. Signal I27/co1 undriven or does not drive anything - clipped. Signal I27/cnt_cia_S1_2 undriven or does not drive anything - clipped. Signal I27/cnt_cia_S0_2 undriven or does not drive anything - clipped. Signal I53/PLLDATO0 undriven or does not drive anything - clipped. Signal I53/PLLDATO1 undriven or does not drive anything - clipped. Signal I53/PLLDATO2 undriven or does not drive anything - clipped. Signal I53/PLLDATO3 undriven or does not drive anything - clipped. Signal I53/PLLDATO4 undriven or does not drive anything - clipped. Signal I53/PLLDATO5 undriven or does not drive anything - clipped. Signal I53/PLLDATO6 undriven or does not drive anything - clipped. Signal I53/PLLDATO7 undriven or does not drive anything - clipped. Signal I53/PLLACK undriven or does not drive anything - clipped. Signal I53/DPHSRC undriven or does not drive anything - clipped. Signal I53/CLKINTFB undriven or does not drive anything - clipped. Signal I53/REFCLK undriven or does not drive anything - clipped. Signal I53/INTLOCK undriven or does not drive anything - clipped. Signal I53/LOCK undriven or does not drive anything - clipped. Signal I53/CLKOS2 undriven or does not drive anything - clipped. Signal I53/CLKOS undriven or does not drive anything - clipped. Signal I52/co2 undriven or does not drive anything - clipped. Signal I52/cnt_cia_S1_3 undriven or does not drive anything - clipped. Signal I52/cnt_cia_S0_3 undriven or does not drive anything - clipped. Signal I69/un2_cnt_1_cry_19_0_COUT undriven or does not drive anything - clipped. Signal I69/un2_cnt_1_cry_0_0_S1 undriven or does not drive anything - clipped. Signal I69/un2_cnt_1_cry_0_0_S0 undriven or does not drive anything - clipped. Signal I69/N_1 undriven or does not drive anything - clipped. Signal I5_SEDSTDBY undriven or does not drive anything - clipped. Block I24 was optimized away. Block I41 was optimized away. Block I40 was optimized away. Block I86 was optimized away. Block I85 was optimized away. Block I84 was optimized away. Block I25 was optimized away. Block I7/LUT4_2 was optimized away. Block I7/GND was optimized away. Block I7/VCC was optimized away. Block I8/VCC was optimized away. Block I8/GND was optimized away. Block I43/VCC was optimized away. Block I43/GND was optimized away. Block I27/VCC was optimized away. Block I27/GND was optimized away. Block I53/GND was optimized away. Block I52/GND was optimized away. Block I52/VCC was optimized away. Block I69/GND was optimized away. Memory Usage PLL/DLL Summary --------------- PLL 1: Pin/Node Value PLL Instance Name: I53/PLLInst_0 PLL Type: EHXPLLJ Input Clock: PIN clk_ext_sal_c Output Clock(P): NODE I53/CLKOP Output Clock(S): NONE Output Clock(S2): NONE Output Clock(S3): PIN,NODE N_27 Feedback Signal: NODE I53/CLKOP Reset Signal: NONE M Divider Reset Signal: NONE C Divider Reset Signal: NONE D Divider Reset Signal: NONE Standby Signal: NONE PLL LOCK signal: NONE PLL Data bus CLK Signal: NONE PLL Data bus Strobe Signal: NONE PLL Data bus Reset Signal: NONE PLL Data bus Write Enable Signal: NONE PLL Data bus Address0: NONE PLL Data bus Address1: NONE PLL Data bus Address2: NONE PLL Data bus Address3: NONE PLL Data bus Address4: NONE PLL Data In bus Data0: NONE PLL Data In bus Data1: NONE PLL Data In bus Data2: NONE PLL Data In bus Data3: NONE PLL Data In bus Data4: NONE PLL Data In bus Data5: NONE PLL Data In bus Data6: NONE PLL Data In bus Data7: NONE PLL Data bus Acknowledge: NONE PLL Data Out bus Data0: NONE PLL Data Out bus Data1: NONE PLL Data Out bus Data2: NONE PLL Data Out bus Data3: NONE PLL Data Out bus Data4: NONE PLL Data Out bus Data5: NONE PLL Data Out bus Data6: NONE PLL Data Out bus Data7: NONE Input Clock Frequency (MHz): 50.0000 Output Clock(P) Frequency (MHz): 10.0000 Output Clock(S) Frequency (MHz): NA Output Clock(S2) Frequency (MHz): NA Output Clock(S3) Frequency (MHz): 0.0173 CLKOP Post Divider A Input: DIVA CLKOS Post Divider B Input: DIVB CLKOS2 Post Divider C Input: DIVC CLKOS3 Post Divider D Input: DIVD Pre Divider A Input: VCO_PHASE Pre Divider B Input: VCO_PHASE Pre Divider C Input: VCO_PHASE Pre Divider D Input: DIVC VCO Bypass A Input: VCO_PHASE VCO Bypass B Input: VCO_PHASE VCO Bypass C Input: VCO_PHASE VCO Bypass D Input: VCO_PHASE FB_MODE: CLKOP CLKI Divider: 5 CLKFB Divider: 1 CLKOP Divider: 27 CLKOS Divider: 1 CLKOS2 Divider: 122 CLKOS3 Divider: 128 Fractional N Divider: 0 CLKOP Desired Phase Shift(degree): 0 CLKOP Trim Option Rising/Falling: RISING CLKOP Trim Option Delay: 0 CLKOS Desired Phase Shift(degree): 0 CLKOS Trim Option Rising/Falling: FALLING CLKOS Trim Option Delay: 0 CLKOS2 Desired Phase Shift(degree): 0 CLKOS3 Desired Phase Shift(degree): 0 OSC Summary ----------- OSC 1: Pin/Node Value OSC Instance Name: I5 OSC Type: OSCH STDBY Input: PIN N_24 OSC Output: NODE N_25 OSC Nominal Frequency (MHz): 2.08 ASIC Components --------------- Instance Name: I5 Type: OSCH Instance Name: I53/PLLInst_0 Type: EHXPLLJ GSR Usage --------- GSR Component: The local reset signal 'Q[20]' of the design has been inferred as Global Set Reset (GSR). The reset signal used for GSR control is 'Q[20]'. GSR Property: The design components with GSR property set to ENABLED will respond to global set reset while the components with GSR property set to DISABLED will not. Components on inferred reset domain with GSR Property disabled -------------------------------------------------------------- These components have the GSR property set to DISABLED and are on the inferred reset domain. The components will respond to the reset signal 'Q[20]' via the local reset on the component and not the GSR component. Type and number of components of the type: Register = 12 Type and instance name of component: Register : I80 Register : I79 Register : I78 Register : I77 Register : I76 Register : I75 Register : I74 Register : I73 Register : I72 Register : I71 Register : I70 Register : I81 Run Time and Memory Usage ------------------------- Total CPU Time: 0 secs Total REAL Time: 0 secs Peak Memory Usage: 34 MB Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2016 Lattice Semiconductor Corporation, All rights reserved.