Project Settings |
---|
Project Name | proj_1 | Implementation Name | esquema_con_gpio |
Top Module | esquema_con_gpio | Pipelining | 1 |
Retiming | 0 | Resource Sharing | 1 |
Fanout Guide | 1000 | Disable I/O Insertion | 0 |
Disable Sequential Optimizations | 0 | Clock Conversion | 1 |
Run Status |
Job Name |
Status |
|
|
|
CPU Time |
Real Time |
Memory |
Date/Time |
(compiler) | Complete |
59 |
278 |
0 |
- |
0m:01s |
- |
30/09/2017 4:33:31 |
(premap) | Complete |
2 |
1 |
0 |
0m:00s |
0m:01s |
144MB |
30/09/2017 4:33:34 |
(fpga_mapper) | Complete |
81 |
15 |
0 |
0m:03s |
0m:03s |
171MB |
30/09/2017 4:33:38 |
Multi-srs Generator |
Complete | | | | | | | 30/09/2017 4:33:33 |
Area Summary |
|
Register bits | 120 |
I/O cells | 20 |
Block RAMs
(v_ram) | 0 |
DSPs
(dsp_used) | 0 |
ORCA LUTs
(total_luts) | 254 |
| |
Timing Summary |
|
Clock Name | Req Freq | Est Freq | Slack |
div2|tdataout0_derived_clock | 1.0 MHz | 136.7 MHz | 1985.372 |
esquema_con_gpio|sal_osc | 1.0 MHz | NA | NA |
System | 1.0 MHz | 76.0 MHz | 986.846 |
Optimizations Summary |
Combined Clock Conversion | 2 / 0 |
| |
|