Project Settings
Project Name proj_1 Implementation Name proyecto_global
Top Module esquema_global Pipelining 1
Retiming 0 Resource Sharing 1
Fanout Guide 1000 Disable I/O Insertion 0
Disable Sequential Optimizations 0 Clock Conversion 1

Run Status
Job Name Status CPU Time Real Time Memory Date/Time
(compiler)Complete 77 376 0 - 0m:05s - 03/10/2017
2:28:48
(premap)Complete 2 4 0 0m:01s 0m:02s 144MB 03/10/2017
2:28:53
(fpga_mapper)Complete 84 25 0 0m:04s 0m:05s 176MB 03/10/2017
2:28:59
Multi-srs Generator Complete0m:01s03/10/2017
2:28:50

Area Summary
Register bits 177 I/O cells 26
Block RAMs (v_ram) 0 DSPs (dsp_used) 0
ORCA LUTs (total_luts) 295

Timing Summary
Clock NameReq FreqEst FreqSlack
div2|tdataout0_derived_clock1.0 MHz128.5 MHz1984.433
esquema_global|N_25_inferred_clock2.1 MHz201.0 MHz475.795
esquema_global|N_33_inferred_clock1.0 MHz165.2 MHz993.946
esquema_global|clk_ext_sal1.0 MHz254.8 MHz996.075
pll1|CLKOS3_inferred_clock1.0 MHz334.2 MHz997.007
System1.0 MHz71.0 MHz985.913

Optimizations Summary
Combined Clock Conversion 2 / 3