PAR: Place And Route Diamond Version 3.8.0.115.3.
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2016 Lattice Semiconductor Corporation,  All rights reserved.
Thu Sep 21 07:06:00 2017

C:/lscc/diamond/3.8/ispfpga\bin\nt\par -f proyecto_global_proyecto_global.p2t
proyecto_global_proyecto_global_map.ncd proyecto_global_proyecto_global.dir
proyecto_global_proyecto_global.prf -gui -msgset C:/TFG/exp1_pll2/promote.xml


Preference file: proyecto_global_proyecto_global.prf.

Cost Table Summary
Level/       Number       Worst        Timing       Worst        Timing       Run          NCD
Cost [ncd]   Unrouted     Slack        Score        Slack(hold)  Score(hold)  Time         Status
----------   --------     -----        ------       -----------  -----------  ----         ------
5_1   *      0            467.448      0            0.857        0            08           Complete


* : Design saved.

Total (real) run time for 1-seed: 8 secs 

par done!

Lattice Place and Route Report for Design "proyecto_global_proyecto_global_map.ncd"
Thu Sep 21 07:06:00 2017


Best Par Run
PAR: Place And Route Diamond Version 3.8.0.115.3.
Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset C:/TFG/exp1_pll2/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF proyecto_global_proyecto_global_map.ncd proyecto_global_proyecto_global.dir/5_1.ncd proyecto_global_proyecto_global.prf
Preference file: proyecto_global_proyecto_global.prf.
Placement level-cost: 5-1.
Routing Iterations: 6

Loading design for application par from file proyecto_global_proyecto_global_map.ncd.
Design name: esquema_global
NCD version: 3.3
Vendor:      LATTICE
Device:      LCMXO2-1200ZE
Package:     TQFP144
Performance: 1
Loading device for application par from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.8/ispfpga.
Package Status:                     Final          Version 1.42.
Performance Hardware Data Status:   Final          Version 34.4.
License checked out.


Ignore Preference Error(s):  True

Device utilization summary:

   PIO (prelim)   25+4(JTAG)/108     27% used
                  25+4(JTAG)/108     27% bonded

   SLICE             71/640          11% used

   GSR                1/1           100% used
   OSC                1/1           100% used
   PLL                1/1           100% used


Number of Signals: 221
Number of Connections: 477

Pin Constraint Summary:
   25 out of 25 pins locked (100% locked).

WARNING - par: PIO driver comp "clk_ext_sal" of PLL "I74/PLLInst_0" CLKI input will be placed on a non-dedicated PIO site "27/PL9A"; therefore, general routing has to be used.
The following 3 signals are selected to use the primary clock routing resources:
    I74/CLKOP (driver: I74/PLLInst_0, clk load #: 0)
    clk_1mz (driver: I74/PLLInst_0, clk load #: 11)
    N_25 (driver: I5, clk load #: 11)


The following 2 signals are selected to use the secondary clock routing resources:
    N_26 (driver: I74/PLLInst_0, clk load #: 6, sr load #: 0, ce load #: 0)
    N_22 (driver: aclr_a1hz, clk load #: 0, sr load #: 11, ce load #: 0)

WARNING - par: Signal "N_22" is selected to use Secondary clock resources. However, its driver comp "aclr_a1hz" is located at "76", which is not a dedicated pin for connecting to Secondary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
Signal Q[20] is selected as Global Set/Reset.
Starting Placer Phase 0.
........
Finished Placer Phase 0.  REAL time: 0 secs 

Starting Placer Phase 1.
..................
Placer score = 17815.
Finished Placer Phase 1.  REAL time: 6 secs 

Starting Placer Phase 2.
.
Placer score =  17713
Finished Placer Phase 2.  REAL time: 6 secs 



Clock Report

Global Clock Resources:
  CLK_PIN    : 0 out of 8 (0%)
  General PIO: 1 out of 108 (0%)
  PLL        : 1 out of 1 (100%)
  DCM        : 0 out of 2 (0%)
  DCC        : 0 out of 8 (0%)

Quadrants All (TL, TR, BL, BR) - Global Clocks:
  PRIMARY "I74/CLKOP" from CLKOP on comp "I74/PLLInst_0" on PLL site "LPLL", clk load = 0
  PRIMARY "clk_1mz" from CLKOS on comp "I74/PLLInst_0" on PLL site "LPLL", clk load = 11
  PRIMARY "N_25" from OSC on comp "I5" on site "OSC", clk load = 11
  SECONDARY "N_26" from CLKOS3 on comp "I74/PLLInst_0" on PLL site "LPLL", clk load = 6, ce load = 0, sr load = 0
  SECONDARY "N_22" from comp "aclr_a1hz" on PIO site "76 (PR10A)", clk load = 0, ce load = 0, sr load = 11

  PRIMARY  : 3 out of 8 (37%)
  SECONDARY: 2 out of 8 (25%)

Edge Clocks:
  No edge clock selected.




I/O Usage Summary (final):
   25 + 4(JTAG) out of 108 (26.9%) PIO sites used.
   25 + 4(JTAG) out of 108 (26.9%) bonded PIO sites used.
   Number of PIO comps: 25; differential: 0.
   Number of Vref pins used: 0.

I/O Bank Usage Summary:
+----------+----------------+------------+-----------+
| I/O Bank | Usage          | Bank Vccio | Bank Vref |
+----------+----------------+------------+-----------+
| 0        | 0 / 28 (  0%)  | -          | -         |
| 1        | 7 / 26 ( 26%)  | 3.3V       | -         |
| 2        | 0 / 28 (  0%)  | -          | -         |
| 3        | 18 / 26 ( 69%) | 3.3V       | -         |
+----------+----------------+------------+-----------+

Total placer CPU time: 5 secs 

Dumping design to file proyecto_global_proyecto_global.dir/5_1.ncd.

0 connections routed; 477 unrouted.
Starting router resource preassignment
WARNING - par: Unable to route net (PIO to PLL_CLKI) with dedicated resource for net clk_ext_sal_c.


Completed router resource preassignment. Real time: 6 secs 

Start NBR router at 07:06:07 09/21/17

*****************************************************************
Info: NBR allows conflicts(one node used by more than one signal)
      in the earlier iterations. In each iteration, it tries to  
      solve the conflicts while keeping the critical connections 
      routed as short as possible. The routing process is said to
      be completed when no conflicts exist and all connections   
      are routed.                                                
Note: NBR uses a different method to calculate timing slacks. The
      worst slack and total negative slack may not be the same as
      that in TRCE report. You should always run TRCE to verify  
      your design.                                               
*****************************************************************

Start NBR special constraint process at 07:06:07 09/21/17

Start NBR section for initial routing at 07:06:07 09/21/17
Level 4, iteration 1
4(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
Estimated worst slack/total negative slack<setup>: 467.448ns/0.000ns; real time: 7 secs 

Info: Initial congestion level at 75% usage is 0
Info: Initial congestion area  at 75% usage is 0 (0.00%)

Start NBR section for normal routing at 07:06:07 09/21/17
Level 4, iteration 1
1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
Estimated worst slack/total negative slack<setup>: 467.448ns/0.000ns; real time: 7 secs 
Level 4, iteration 2
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
Estimated worst slack/total negative slack<setup>: 467.448ns/0.000ns; real time: 7 secs 

Start NBR section for setup/hold timing optimization with effort level 3 at 07:06:07 09/21/17

Start NBR section for re-routing at 07:06:07 09/21/17
Level 4, iteration 1
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
Estimated worst slack/total negative slack<setup>: 467.448ns/0.000ns; real time: 7 secs 

Start NBR section for post-routing at 07:06:07 09/21/17

End NBR router with 0 unrouted connection

NBR Summary
-----------
  Number of unrouted connections : 0 (0.00%)
  Number of connections with timing violations : 0 (0.00%)
  Estimated worst slack<setup> : 467.448ns
  Timing score<setup> : 0
-----------
Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.



Total CPU time 7 secs 
Total REAL time: 8 secs 
Completely routed.
End of route.  477 routed (100.00%); 0 unrouted.

Hold time timing score: 0, hold timing errors: 0

Timing score: 0 

Dumping design to file proyecto_global_proyecto_global.dir/5_1.ncd.


All signals are completely routed.


PAR_SUMMARY::Run status = completed
PAR_SUMMARY::Number of unrouted conns = 0
PAR_SUMMARY::Worst  slack<setup/<ns>> = 467.448
PAR_SUMMARY::Timing score<setup/<ns>> = 0.000
PAR_SUMMARY::Worst  slack<hold /<ns>> = 0.857
PAR_SUMMARY::Timing score<hold /<ns>> = 0.000
PAR_SUMMARY::Number of errors = 0

Total CPU  time to completion: 7 secs 
Total REAL time to completion: 8 secs 

par done!

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2016 Lattice Semiconductor Corporation,  All rights reserved.