Setting log file to 'C:/TFG/exp7/proy_glob/hdla_gen_hierarchy.html'.
Starting: parse design source files
(VHDL-1481) Analyzing VHDL file C:/lscc/diamond/3.8/ispfpga/vhdl_packages/standard.vhd
INFO - C:/lscc/diamond/3.8/ispfpga/vhdl_packages/standard.vhd(9,9-9,17) (VHDL-1014) analyzing package standard
(VHDL-1481) Analyzing VHDL file C:/lscc/diamond/3.8/ispfpga/vhdl_packages/std_1164.vhd
INFO - C:/lscc/diamond/3.8/ispfpga/vhdl_packages/std_1164.vhd(15,9-15,23) (VHDL-1014) analyzing package std_logic_1164
INFO - C:/lscc/diamond/3.8/ispfpga/vhdl_packages/std_1164.vhd(178,14-178,28) (VHDL-1013) analyzing package body std_logic_1164
(VHDL-1481) Analyzing VHDL file C:/lscc/diamond/3.8/ispfpga/vhdl_packages/mgc_qsim.vhd
INFO - C:/lscc/diamond/3.8/ispfpga/vhdl_packages/mgc_qsim.vhd(18,9-18,19) (VHDL-1014) analyzing package qsim_logic
INFO - C:/lscc/diamond/3.8/ispfpga/vhdl_packages/mgc_qsim.vhd(753,14-753,24) (VHDL-1013) analyzing package body qsim_logic
(VHDL-1481) Analyzing VHDL file C:/lscc/diamond/3.8/ispfpga/vhdl_packages/numeric_bit.vhd
INFO - C:/lscc/diamond/3.8/ispfpga/vhdl_packages/numeric_bit.vhd(54,9-54,20) (VHDL-1014) analyzing package numeric_bit
INFO - C:/lscc/diamond/3.8/ispfpga/vhdl_packages/numeric_bit.vhd(834,14-834,25) (VHDL-1013) analyzing package body numeric_bit
(VHDL-1481) Analyzing VHDL file C:/lscc/diamond/3.8/ispfpga/vhdl_packages/numeric_std.vhd
INFO - C:/lscc/diamond/3.8/ispfpga/vhdl_packages/numeric_std.vhd(57,9-57,20) (VHDL-1014) analyzing package numeric_std
INFO - C:/lscc/diamond/3.8/ispfpga/vhdl_packages/numeric_std.vhd(874,14-874,25) (VHDL-1013) analyzing package body numeric_std
(VHDL-1481) Analyzing VHDL file C:/lscc/diamond/3.8/ispfpga/vhdl_packages/textio.vhd
INFO - C:/lscc/diamond/3.8/ispfpga/vhdl_packages/textio.vhd(13,9-13,15) (VHDL-1014) analyzing package textio
INFO - C:/lscc/diamond/3.8/ispfpga/vhdl_packages/textio.vhd(114,14-114,20) (VHDL-1013) analyzing package body textio
(VHDL-1481) Analyzing VHDL file C:/lscc/diamond/3.8/ispfpga/vhdl_packages/std_logic_textio.vhd
INFO - C:/lscc/diamond/3.8/ispfpga/vhdl_packages/std_logic_textio.vhd(26,9-26,25) (VHDL-1014) analyzing package std_logic_textio
INFO - C:/lscc/diamond/3.8/ispfpga/vhdl_packages/std_logic_textio.vhd(72,14-72,30) (VHDL-1013) analyzing package body std_logic_textio
(VHDL-1481) Analyzing VHDL file C:/lscc/diamond/3.8/ispfpga/vhdl_packages/syn_attr.vhd
INFO - C:/lscc/diamond/3.8/ispfpga/vhdl_packages/syn_attr.vhd(39,9-39,19) (VHDL-1014) analyzing package attributes
(VHDL-1481) Analyzing VHDL file C:/lscc/diamond/3.8/ispfpga/vhdl_packages/syn_misc.vhd
INFO - C:/lscc/diamond/3.8/ispfpga/vhdl_packages/syn_misc.vhd(30,9-30,23) (VHDL-1014) analyzing package std_logic_misc
INFO - C:/lscc/diamond/3.8/ispfpga/vhdl_packages/syn_misc.vhd(182,14-182,28) (VHDL-1013) analyzing package body std_logic_misc
INFO - ./.__tmp_vxr_0_(56,9-56,18) (VHDL-1014) analyzing package math_real
INFO - ./.__tmp_vxr_0_(685,14-685,23) (VHDL-1013) analyzing package body math_real
(VHDL-1481) Analyzing VHDL file C:/lscc/diamond/3.8/ispfpga/vhdl_packages/mixed_lang_vltype.vhd
INFO - C:/lscc/diamond/3.8/ispfpga/vhdl_packages/mixed_lang_vltype.vhd(9,9-9,17) (VHDL-1014) analyzing package vl_types
INFO - C:/lscc/diamond/3.8/ispfpga/vhdl_packages/mixed_lang_vltype.vhd(88,14-88,22) (VHDL-1013) analyzing package body vl_types
(VHDL-1481) Analyzing VHDL file C:/lscc/diamond/3.8/ispfpga/vhdl_packages/syn_arit.vhd
INFO - C:/lscc/diamond/3.8/ispfpga/vhdl_packages/syn_arit.vhd(25,9-25,24) (VHDL-1014) analyzing package std_logic_arith
INFO - C:/lscc/diamond/3.8/ispfpga/vhdl_packages/syn_arit.vhd(206,14-206,29) (VHDL-1013) analyzing package body std_logic_arith
(VHDL-1481) Analyzing VHDL file C:/lscc/diamond/3.8/ispfpga/vhdl_packages/syn_sign.vhd
INFO - C:/lscc/diamond/3.8/ispfpga/vhdl_packages/syn_sign.vhd(35,9-35,25) (VHDL-1014) analyzing package std_logic_signed
INFO - C:/lscc/diamond/3.8/ispfpga/vhdl_packages/syn_sign.vhd(96,14-96,30) (VHDL-1013) analyzing package body std_logic_signed
(VHDL-1481) Analyzing VHDL file C:/lscc/diamond/3.8/ispfpga/vhdl_packages/syn_unsi.vhd
INFO - C:/lscc/diamond/3.8/ispfpga/vhdl_packages/syn_unsi.vhd(35,9-35,27) (VHDL-1014) analyzing package std_logic_unsigned
INFO - C:/lscc/diamond/3.8/ispfpga/vhdl_packages/syn_unsi.vhd(94,14-94,32) (VHDL-1013) analyzing package body std_logic_unsigned
(VHDL-1481) Analyzing VHDL file C:/lscc/diamond/3.8/ispfpga/vhdl_packages/synattr.vhd
INFO - C:/lscc/diamond/3.8/ispfpga/vhdl_packages/synattr.vhd(50,9-50,19) (VHDL-1014) analyzing package attributes
(VERI-1482) Analyzing Verilog file C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v
(VERI-1482) Analyzing Verilog file C:/TFG/exp7/proy_glob/proy_glob.v
(VERI-1482) Analyzing Verilog file C:/TFG/exp7/mic32/soc/mic32.v
INFO - C:/TFG/exp7/mic32/soc/mic32.v(46,10-46,25) (VERI-1328) analyzing included file C:/TFG/exp7/mic32/soc/system_conf.v
INFO - C:/TFG/exp7/mic32/soc/mic32.v(327,10-327,65) (VERI-1328) analyzing included file C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_include_all.v
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_include_all.v(52,10-52,21) (VERI-1328) analyzing included file C:/TFG/exp7/mic32/soc/pmi_def.v
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_include_all.v(54,10-54,25) (VERI-1328) analyzing included file C:/TFG/exp7/mic32/soc/system_conf.v
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_include_all.v(57,12-57,56) (VERI-1328) analyzing included file C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/typeb.v
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_include_all.v(58,12-58,56) (VERI-1328) analyzing included file C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/typea.v
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_include_all.v(59,12-59,61) (VERI-1328) analyzing included file C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/jtag_cores.v
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/jtag_cores.v(53,10-53,25) (VERI-1328) analyzing included file C:/TFG/exp7/mic32/soc/system_conf.v
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/jtag_cores.v(54,10-54,26) (VERI-1328) analyzing included file C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_include.v
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_include.v(60,10-60,25) (VERI-1328) analyzing included file C:/TFG/exp7/mic32/soc/system_conf.v
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_include_all.v(60,12-60,60) (VERI-1328) analyzing included file C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/jtag_lm32.v
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_include_all.v(61,12-61,60) (VERI-1328) analyzing included file C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_jtag.v
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_jtag.v(52,10-52,26) (VERI-1328) analyzing included file C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_include.v
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_include_all.v(64,10-64,60) (VERI-1328) analyzing included file C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_addsub.v
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_addsub.v(49,10-49,26) (VERI-1328) analyzing included file C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_include.v
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_include_all.v(65,10-65,59) (VERI-1328) analyzing included file C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_adder.v
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_adder.v(50,10-50,26) (VERI-1328) analyzing included file C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_include.v
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_include_all.v(66,10-66,57) (VERI-1328) analyzing included file C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_cpu.v
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_cpu.v(94,10-94,26) (VERI-1328) analyzing included file C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_include.v
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_cpu.v(791,10-791,28) (VERI-1328) analyzing included file C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_functions.v
WARNING - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_cpu.v(653,10-653,54) (VERI-1407) attribute target identifier preserve_driver not found in this scope
WARNING - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_cpu.v(652,10-652,54) (VERI-1407) attribute target identifier preserve_signal not found in this scope
WARNING - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_functions.v(54,9-54,14) (VERI-1214) assignment to input value
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_include_all.v(67,10-67,60) (VERI-1328) analyzing included file C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_dcache.v
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_dcache.v(52,10-52,26) (VERI-1328) analyzing included file C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_include.v
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_dcache.v(203,10-203,28) (VERI-1328) analyzing included file C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_functions.v
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_include_all.v(68,10-68,59) (VERI-1328) analyzing included file C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_debug.v
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_debug.v(53,10-53,26) (VERI-1328) analyzing included file C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_include.v
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_debug.v(186,10-186,28) (VERI-1328) analyzing included file C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_functions.v
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_include_all.v(69,10-69,61) (VERI-1328) analyzing included file C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_decoder.v
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_decoder.v(56,10-56,26) (VERI-1328) analyzing included file C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_include.v
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_decoder.v(336,10-336,28) (VERI-1328) analyzing included file C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_functions.v
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_include_all.v(70,10-70,60) (VERI-1328) analyzing included file C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_icache.v
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_icache.v(57,10-57,26) (VERI-1328) analyzing included file C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_include.v
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_icache.v(208,10-208,28) (VERI-1328) analyzing included file C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_functions.v
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_include_all.v(71,10-71,70) (VERI-1328) analyzing included file C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_instruction_unit.v
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_instruction_unit.v(71,10-71,26) (VERI-1328) analyzing included file C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_include.v
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_instruction_unit.v(380,10-380,28) (VERI-1328) analyzing included file C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_functions.v
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_include_all.v(72,10-72,63) (VERI-1328) analyzing included file C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_interrupt.v
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_interrupt.v(50,10-50,26) (VERI-1328) analyzing included file C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_include.v
WARNING - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_interrupt.v(130,10-130,49) (VERI-1407) attribute target identifier preserve_signal not found in this scope
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_include_all.v(73,10-73,69) (VERI-1328) analyzing included file C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_load_store_unit.v
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_load_store_unit.v(63,10-63,26) (VERI-1328) analyzing included file C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_include.v
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_load_store_unit.v(283,10-283,28) (VERI-1328) analyzing included file C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_functions.v
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_include_all.v(74,10-74,62) (VERI-1328) analyzing included file C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_logic_op.v
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_logic_op.v(50,10-50,26) (VERI-1328) analyzing included file C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_include.v
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_include_all.v(82,12-82,63) (VERI-1328) analyzing included file C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_shifter.v
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_shifter.v(50,10-50,26) (VERI-1328) analyzing included file C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_include.v
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_include_all.v(84,10-84,57) (VERI-1328) analyzing included file C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_top.v
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_top.v(52,10-52,26) (VERI-1328) analyzing included file C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_include.v
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_top.v(277,10-277,28) (VERI-1328) analyzing included file C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_functions.v
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_include_all.v(86,12-86,63) (VERI-1328) analyzing included file C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_monitor.v
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_monitor.v(50,10-50,25) (VERI-1328) analyzing included file C:/TFG/exp7/mic32/soc/system_conf.v
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_monitor.v(51,10-51,26) (VERI-1328) analyzing included file C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_include.v
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_include_all.v(87,12-87,67) (VERI-1328) analyzing included file C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_monitor_ram.v
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_monitor_ram.v(51,10-51,25) (VERI-1328) analyzing included file C:/TFG/exp7/mic32/soc/system_conf.v
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_include_all.v(102,12-102,59) (VERI-1328) analyzing included file C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_ram.v
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_ram.v(55,10-55,26) (VERI-1328) analyzing included file C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_include.v
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_include_all.v(104,12-104,61) (VERI-1328) analyzing included file C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_trace.v
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_trace.v(52,10-52,26) (VERI-1328) analyzing included file C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_include.v
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_trace.v(53,10-53,25) (VERI-1328) analyzing included file C:/TFG/exp7/mic32/soc/system_conf.v
INFO - C:/TFG/exp7/mic32/soc/mic32.v(328,10-328,49) (VERI-1328) analyzing included file C:/TFG/exp7/mic32/soc/../components/gpio/rtl/verilog/gpio.v
INFO - C:/TFG/exp7/mic32/soc/../components/gpio/rtl/verilog/gpio.v(79,10-79,25) (VERI-1328) analyzing included file C:/TFG/exp7/mic32/soc/system_conf.v
WARNING - C:/TFG/exp7/mic32/soc/../components/gpio/rtl/verilog/gpio.v(176,4-176,23) (VERI-1199) parameter declaration becomes local in gpio with formal parameter declaration list
INFO - C:/TFG/exp7/mic32/soc/mic32.v(329,10-329,49) (VERI-1328) analyzing included file C:/TFG/exp7/mic32/soc/../components/gpio/rtl/verilog/tpio.v
INFO - C:/TFG/exp7/mic32/soc/../components/gpio/rtl/verilog/tpio.v(65,10-65,25) (VERI-1328) analyzing included file C:/TFG/exp7/mic32/soc/system_conf.v
WARNING - C:/TFG/exp7/mic32/soc/../components/gpio/rtl/verilog/tpio.v(87,4-87,23) (VERI-1199) parameter declaration becomes local in tpio with formal parameter declaration list
INFO - C:/TFG/exp7/mic32/soc/mic32.v(330,10-330,60) (VERI-1328) analyzing included file C:/TFG/exp7/mic32/soc/../components/asram_top/rtl/verilog/asram_core.v
INFO - C:/TFG/exp7/mic32/soc/../components/asram_top/rtl/verilog/asram_core.v(64,11-64,26) (VERI-1328) analyzing included file C:/TFG/exp7/mic32/soc/system_conf.v
WARNING - C:/TFG/exp7/mic32/soc/../components/asram_top/rtl/verilog/asram_core.v(112,4-112,30) (VERI-1199) parameter declaration becomes local in asram_core with formal parameter declaration list
WARNING - C:/TFG/exp7/mic32/soc/../components/asram_top/rtl/verilog/asram_core.v(113,4-113,30) (VERI-1199) parameter declaration becomes local in asram_core with formal parameter declaration list
WARNING - C:/TFG/exp7/mic32/soc/../components/asram_top/rtl/verilog/asram_core.v(114,4-114,30) (VERI-1199) parameter declaration becomes local in asram_core with formal parameter declaration list
INFO - C:/TFG/exp7/mic32/soc/mic32.v(331,10-331,59) (VERI-1328) analyzing included file C:/TFG/exp7/mic32/soc/../components/asram_top/rtl/verilog/asram_top.v
INFO - C:/TFG/exp7/mic32/soc/../components/asram_top/rtl/verilog/asram_top.v(56,10-56,25) (VERI-1328) analyzing included file C:/TFG/exp7/mic32/soc/system_conf.v
INFO - C:/TFG/exp7/mic32/soc/mic32.v(332,10-332,65) (VERI-1328) analyzing included file C:/TFG/exp7/mic32/soc/../components/parallel_flash/rtl/verilog/flash_core.v
INFO - C:/TFG/exp7/mic32/soc/../components/parallel_flash/rtl/verilog/flash_core.v(61,11-61,26) (VERI-1328) analyzing included file C:/TFG/exp7/mic32/soc/system_conf.v
WARNING - C:/TFG/exp7/mic32/soc/../components/parallel_flash/rtl/verilog/flash_core.v(91,4-91,67) (VERI-1199) parameter declaration becomes local in flash_core with formal parameter declaration list
WARNING - C:/TFG/exp7/mic32/soc/../components/parallel_flash/rtl/verilog/flash_core.v(92,4-92,66) (VERI-1199) parameter declaration becomes local in flash_core with formal parameter declaration list
INFO - C:/TFG/exp7/mic32/soc/mic32.v(333,10-333,69) (VERI-1328) analyzing included file C:/TFG/exp7/mic32/soc/../components/parallel_flash/rtl/verilog/parallel_flash.v
INFO - C:/TFG/exp7/mic32/soc/../components/parallel_flash/rtl/verilog/parallel_flash.v(60,10-60,25) (VERI-1328) analyzing included file C:/TFG/exp7/mic32/soc/system_conf.v
(VHDL-1481) Analyzing VHDL file C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.vhd
(VHDL-1481) Analyzing VHDL file C:/TFG/exp7/mic32/soc/mic32_vhd.vhd
INFO - C:/TFG/exp7/mic32/soc/mic32_vhd.vhd(4,8-4,17) (VHDL-1012) analyzing entity mic32_vhd
INFO - C:/TFG/exp7/mic32/soc/mic32_vhd.vhd(23,14-23,25) (VHDL-1010) analyzing architecture mic32_vhd_a
(VHDL-1481) Analyzing VHDL file C:/TFG/exp7/div2.vhd
INFO - C:/TFG/exp7/div2.vhd(14,8-14,12) (VHDL-1012) analyzing entity div2
INFO - C:/TFG/exp7/div2.vhd(22,14-22,23) (VHDL-1010) analyzing architecture structure
INFO - C:/TFG/exp7/proy_glob/proy_glob.v(3,8-3,17) (VERI-1018) compiling module proy_glob
INFO - C:/TFG/exp7/proy_glob/proy_glob.v(3,1-40,10) (VERI-9000) elaborating module 'proy_glob'
INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(498,1-501,10) (VERI-9000) elaborating module 'IB_uniq_1'
INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(857,1-860,10) (VERI-9000) elaborating module 'OB_uniq_1'
INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(857,1-860,10) (VERI-9000) elaborating module 'OB_uniq_2'
INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(857,1-860,10) (VERI-9000) elaborating module 'OB_uniq_3'
INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(857,1-860,10) (VERI-9000) elaborating module 'OB_uniq_4'
INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(857,1-860,10) (VERI-9000) elaborating module 'OB_uniq_5'
INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(857,1-860,10) (VERI-9000) elaborating module 'OB_uniq_6'
INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(857,1-860,10) (VERI-9000) elaborating module 'OB_uniq_7'
INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(857,1-860,10) (VERI-9000) elaborating module 'OB_uniq_8'
INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(857,1-860,10) (VERI-9000) elaborating module 'OB_uniq_9'
INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(857,1-860,10) (VERI-9000) elaborating module 'OB_uniq_10'
INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1120,1-1122,10) (VERI-9000) elaborating module 'VHI_uniq_1'
INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1120,1-1122,10) (VERI-9000) elaborating module 'VHI_uniq_2'
INFO - C:/TFG/exp7/proy_glob/proy_glob.v(24,1-24,53) (VERI-1231) going to vhdl side to elaborate module div2
INFO - C:/TFG/exp7/div2.vhd(14,8-14,12) (VHDL-1067) elaborating div2_uniq_0(Structure)
INFO - C:/TFG/exp7/div2.vhd(60,5-62,27) (VHDL-1399) going to verilog side to elaborate module FD1P3DX
INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,8-187,15) (VERI-1018) compiling module FD1P3DX_uniq_1
INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_1'
INFO - C:/TFG/exp7/div2.vhd(60,5-62,27) (VHDL-1400) back to vhdl to continue elaboration
INFO - C:/TFG/exp7/div2.vhd(64,5-65,33) (VHDL-1399) going to verilog side to elaborate module VHI
INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1120,8-1120,11) (VERI-1018) compiling module VHI_uniq_3
INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1120,1-1122,10) (VERI-9000) elaborating module 'VHI_uniq_3'
INFO - C:/TFG/exp7/div2.vhd(64,5-65,33) (VHDL-1400) back to vhdl to continue elaboration
INFO - C:/TFG/exp7/div2.vhd(67,5-70,23) (VHDL-1399) going to verilog side to elaborate module FADD2B
INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(138,8-138,14) (VERI-1018) compiling module FADD2B_uniq_1
INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(138,1-142,10) (VERI-9000) elaborating module 'FADD2B_uniq_1'
INFO - C:/TFG/exp7/div2.vhd(67,5-70,23) (VHDL-1400) back to vhdl to continue elaboration
INFO - C:/TFG/exp7/div2.vhd(72,5-74,40) (VHDL-1399) going to verilog side to elaborate module CU2
INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(129,8-129,11) (VERI-1018) compiling module CU2_uniq_1
INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(129,1-136,10) (VERI-9000) elaborating module 'CU2_uniq_1'
INFO - C:/TFG/exp7/div2.vhd(72,5-74,40) (VHDL-1400) back to vhdl to continue elaboration
INFO - C:/TFG/exp7/div2.vhd(76,5-77,33) (VHDL-1399) going to verilog side to elaborate module VLO
INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1124,8-1124,11) (VERI-1018) compiling module VLO_uniq_1
INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1124,1-1126,10) (VERI-9000) elaborating module 'VLO_uniq_1'
INFO - C:/TFG/exp7/div2.vhd(76,5-77,33) (VHDL-1400) back to vhdl to continue elaboration
INFO - C:/TFG/exp7/proy_glob/proy_glob.v(24,1-24,53) (VERI-1232) back to verilog to continue elaboration
INFO - C:/TFG/exp7/proy_glob/proy_glob.v(38,1-38,67) (VERI-1231) going to vhdl side to elaborate module mic32_vhd
INFO - C:/TFG/exp7/mic32/soc/mic32_vhd.vhd(4,8-4,17) (VHDL-1067) elaborating mic32_vhd_uniq_0(mic32_vhd_a)
INFO - C:/TFG/exp7/mic32/soc/mic32_vhd.vhd(48,1-64,6) (VHDL-1399) going to verilog side to elaborate module mic32
INFO - C:/TFG/exp7/mic32/soc/mic32.v(336,8-336,13) (VERI-1018) compiling module mic32_uniq_1
INFO - C:/TFG/exp7/mic32/soc/mic32.v(336,1-764,10) (VERI-9000) elaborating module 'mic32_uniq_1'
INFO - C:/TFG/exp7/mic32/soc/mic32.v(48,1-325,10) (VERI-9000) elaborating module 'arbiter2_uniq_1'
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_top.v(58,1-435,10) (VERI-9000) elaborating module 'lm32_top_uniq_1'
INFO - C:/TFG/exp7/mic32/soc/../components/gpio/rtl/verilog/gpio.v(80,1-1887,10) (VERI-9000) elaborating module 'gpio_uniq_1'
INFO - C:/TFG/exp7/mic32/soc/../components/asram_top/rtl/verilog/asram_top.v(58,1-139,10) (VERI-9000) elaborating module 'asram_top_uniq_1'
INFO - C:/TFG/exp7/mic32/soc/../components/parallel_flash/rtl/verilog/parallel_flash.v(62,1-210,10) (VERI-9000) elaborating module 'parallel_flash_uniq_1'
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_cpu.v(100,1-2788,10) (VERI-9000) elaborating module 'lm32_cpu_uniq_1'
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_monitor.v(57,1-190,10) (VERI-9000) elaborating module 'lm32_monitor_uniq_1'
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/jtag_cores.v(75,1-154,10) (VERI-9000) elaborating module 'jtag_cores_uniq_1'
INFO - C:/TFG/exp7/mic32/soc/../components/asram_top/rtl/verilog/asram_core.v(66,1-693,10) (VERI-9000) elaborating module 'asram_core_uniq_1'
INFO - C:/TFG/exp7/mic32/soc/../components/parallel_flash/rtl/verilog/flash_core.v(63,1-429,10) (VERI-9000) elaborating module 'flash_core_uniq_1'
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_instruction_unit.v(77,1-889,10) (VERI-9000) elaborating module 'lm32_instruction_unit_uniq_1'
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_decoder.v(113,1-603,10) (VERI-9000) elaborating module 'lm32_decoder_uniq_1'
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_load_store_unit.v(69,1-827,10) (VERI-9000) elaborating module 'lm32_load_store_unit_uniq_1'
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_adder.v(56,1-135,10) (VERI-9000) elaborating module 'lm32_adder_uniq_1'
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_logic_op.v(56,1-96,10) (VERI-9000) elaborating module 'lm32_logic_op_uniq_1'
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_shifter.v(56,1-155,10) (VERI-9000) elaborating module 'lm32_shifter_uniq_1'
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_interrupt.v(56,1-355,10) (VERI-9000) elaborating module 'lm32_interrupt_uniq_1'
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_jtag.v(87,1-587,10) (VERI-9000) elaborating module 'lm32_jtag_uniq_1'
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_debug.v(69,1-367,10) (VERI-9000) elaborating module 'lm32_debug_uniq_1'
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_monitor_ram.v(53,1-2222,10) (VERI-9000) elaborating module 'lm32_monitor_ram_uniq_1'
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/jtag_lm32.v(51,1-3083,10) (VERI-9000) elaborating module 'jtag_lm32_uniq_1'
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_icache.v(86,1-506,10) (VERI-9000) elaborating module 'lm32_icache_uniq_1'
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_dcache.v(80,1-551,10) (VERI-9000) elaborating module 'lm32_dcache_uniq_1'
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_addsub.v(55,1-114,10) (VERI-9000) elaborating module 'lm32_addsub_uniq_1'
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/typea.v(65,1-102,10) (VERI-9000) elaborating module 'TYPEA_uniq_1'
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/typea.v(65,1-102,10) (VERI-9000) elaborating module 'TYPEA_uniq_2'
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/typea.v(65,1-102,10) (VERI-9000) elaborating module 'TYPEA_uniq_3'
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/typea.v(65,1-102,10) (VERI-9000) elaborating module 'TYPEA_uniq_4'
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/typea.v(65,1-102,10) (VERI-9000) elaborating module 'TYPEA_uniq_5'
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/typea.v(65,1-102,10) (VERI-9000) elaborating module 'TYPEA_uniq_6'
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/typea.v(65,1-102,10) (VERI-9000) elaborating module 'TYPEA_uniq_7'
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/typea.v(65,1-102,10) (VERI-9000) elaborating module 'TYPEA_uniq_8'
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/typea.v(65,1-102,10) (VERI-9000) elaborating module 'TYPEA_uniq_9'
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/typea.v(65,1-102,10) (VERI-9000) elaborating module 'TYPEA_uniq_10'
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/typea.v(65,1-102,10) (VERI-9000) elaborating module 'TYPEA_uniq_11'
INFO - C:/TFG/exp7/mic32/soc/mic32.v(336,1-764,10) (VERI-9000) elaborating module 'mic32_uniq_1'
INFO - C:/TFG/exp7/mic32/soc/mic32.v(48,1-325,10) (VERI-9000) elaborating module 'arbiter2_uniq_1'
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_top.v(58,1-435,10) (VERI-9000) elaborating module 'lm32_top_uniq_1'
INFO - C:/TFG/exp7/mic32/soc/../components/gpio/rtl/verilog/gpio.v(80,1-1887,10) (VERI-9000) elaborating module 'gpio_uniq_1'
INFO - C:/TFG/exp7/mic32/soc/../components/asram_top/rtl/verilog/asram_top.v(58,1-139,10) (VERI-9000) elaborating module 'asram_top_uniq_1'
INFO - C:/TFG/exp7/mic32/soc/../components/parallel_flash/rtl/verilog/parallel_flash.v(62,1-210,10) (VERI-9000) elaborating module 'parallel_flash_uniq_1'
INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(82,1-87,10) (VERI-9000) elaborating module 'BB_uniq_1'
INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(82,1-87,10) (VERI-9000) elaborating module 'BB_uniq_2'
INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(82,1-87,10) (VERI-9000) elaborating module 'BB_uniq_3'
INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(82,1-87,10) (VERI-9000) elaborating module 'BB_uniq_4'
INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(82,1-87,10) (VERI-9000) elaborating module 'BB_uniq_5'
INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(82,1-87,10) (VERI-9000) elaborating module 'BB_uniq_6'
INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(82,1-87,10) (VERI-9000) elaborating module 'BB_uniq_7'
INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(82,1-87,10) (VERI-9000) elaborating module 'BB_uniq_8'
INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(82,1-87,10) (VERI-9000) elaborating module 'BB_uniq_9'
INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(82,1-87,10) (VERI-9000) elaborating module 'BB_uniq_10'
INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(82,1-87,10) (VERI-9000) elaborating module 'BB_uniq_11'
INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(82,1-87,10) (VERI-9000) elaborating module 'BB_uniq_12'
INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(82,1-87,10) (VERI-9000) elaborating module 'BB_uniq_13'
INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(82,1-87,10) (VERI-9000) elaborating module 'BB_uniq_14'
INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(82,1-87,10) (VERI-9000) elaborating module 'BB_uniq_15'
INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(82,1-87,10) (VERI-9000) elaborating module 'BB_uniq_16'
INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(82,1-87,10) (VERI-9000) elaborating module 'BB_uniq_17'
INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(82,1-87,10) (VERI-9000) elaborating module 'BB_uniq_18'
INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(82,1-87,10) (VERI-9000) elaborating module 'BB_uniq_19'
INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(82,1-87,10) (VERI-9000) elaborating module 'BB_uniq_20'
INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(82,1-87,10) (VERI-9000) elaborating module 'BB_uniq_21'
INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(82,1-87,10) (VERI-9000) elaborating module 'BB_uniq_22'
INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(82,1-87,10) (VERI-9000) elaborating module 'BB_uniq_23'
INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(82,1-87,10) (VERI-9000) elaborating module 'BB_uniq_24'
INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(82,1-87,10) (VERI-9000) elaborating module 'BB_uniq_25'
INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(82,1-87,10) (VERI-9000) elaborating module 'BB_uniq_26'
INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(82,1-87,10) (VERI-9000) elaborating module 'BB_uniq_27'
INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(82,1-87,10) (VERI-9000) elaborating module 'BB_uniq_28'
INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(82,1-87,10) (VERI-9000) elaborating module 'BB_uniq_29'
INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(82,1-87,10) (VERI-9000) elaborating module 'BB_uniq_30'
INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(82,1-87,10) (VERI-9000) elaborating module 'BB_uniq_31'
INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(82,1-87,10) (VERI-9000) elaborating module 'BB_uniq_32'
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_cpu.v(100,1-2788,10) (VERI-9000) elaborating module 'lm32_cpu_uniq_1'
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_monitor.v(57,1-190,10) (VERI-9000) elaborating module 'lm32_monitor_uniq_1'
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/jtag_cores.v(75,1-154,10) (VERI-9000) elaborating module 'jtag_cores_uniq_1'
INFO - C:/TFG/exp7/mic32/soc/../components/asram_top/rtl/verilog/asram_core.v(66,1-693,10) (VERI-9000) elaborating module 'asram_core_uniq_1'
INFO - C:/TFG/exp7/mic32/soc/../components/parallel_flash/rtl/verilog/flash_core.v(63,1-429,10) (VERI-9000) elaborating module 'flash_core_uniq_1'
INFO - C:/TFG/exp7/mic32/soc/../components/gpio/rtl/verilog/tpio.v(66,1-189,10) (VERI-9000) elaborating module 'tpio_uniq_1'
INFO - C:/TFG/exp7/mic32/soc/../components/gpio/rtl/verilog/tpio.v(66,1-189,10) (VERI-9000) elaborating module 'tpio_uniq_2'
INFO - C:/TFG/exp7/mic32/soc/../components/gpio/rtl/verilog/tpio.v(66,1-189,10) (VERI-9000) elaborating module 'tpio_uniq_3'
INFO - C:/TFG/exp7/mic32/soc/../components/gpio/rtl/verilog/tpio.v(66,1-189,10) (VERI-9000) elaborating module 'tpio_uniq_4'
INFO - C:/TFG/exp7/mic32/soc/../components/gpio/rtl/verilog/tpio.v(66,1-189,10) (VERI-9000) elaborating module 'tpio_uniq_5'
INFO - C:/TFG/exp7/mic32/soc/../components/gpio/rtl/verilog/tpio.v(66,1-189,10) (VERI-9000) elaborating module 'tpio_uniq_6'
INFO - C:/TFG/exp7/mic32/soc/../components/gpio/rtl/verilog/tpio.v(66,1-189,10) (VERI-9000) elaborating module 'tpio_uniq_7'
INFO - C:/TFG/exp7/mic32/soc/../components/gpio/rtl/verilog/tpio.v(66,1-189,10) (VERI-9000) elaborating module 'tpio_uniq_8'
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_instruction_unit.v(77,1-889,10) (VERI-9000) elaborating module 'lm32_instruction_unit_uniq_1'
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_decoder.v(113,1-603,10) (VERI-9000) elaborating module 'lm32_decoder_uniq_1'
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_load_store_unit.v(69,1-827,10) (VERI-9000) elaborating module 'lm32_load_store_unit_uniq_1'
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_adder.v(56,1-135,10) (VERI-9000) elaborating module 'lm32_adder_uniq_1'
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_logic_op.v(56,1-96,10) (VERI-9000) elaborating module 'lm32_logic_op_uniq_1'
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_shifter.v(56,1-155,10) (VERI-9000) elaborating module 'lm32_shifter_uniq_1'
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_interrupt.v(56,1-355,10) (VERI-9000) elaborating module 'lm32_interrupt_uniq_1'
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_jtag.v(87,1-587,10) (VERI-9000) elaborating module 'lm32_jtag_uniq_1'
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_debug.v(69,1-367,10) (VERI-9000) elaborating module 'lm32_debug_uniq_1'
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_monitor_ram.v(53,1-2222,10) (VERI-9000) elaborating module 'lm32_monitor_ram_uniq_1'
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/jtag_lm32.v(51,1-3083,10) (VERI-9000) elaborating module 'jtag_lm32_uniq_1'
INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(82,1-87,10) (VERI-9000) elaborating module 'BB_uniq_33'
INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(82,1-87,10) (VERI-9000) elaborating module 'BB_uniq_34'
INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(82,1-87,10) (VERI-9000) elaborating module 'BB_uniq_35'
INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(82,1-87,10) (VERI-9000) elaborating module 'BB_uniq_36'
INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(82,1-87,10) (VERI-9000) elaborating module 'BB_uniq_37'
INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(82,1-87,10) (VERI-9000) elaborating module 'BB_uniq_38'
INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(82,1-87,10) (VERI-9000) elaborating module 'BB_uniq_39'
INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(82,1-87,10) (VERI-9000) elaborating module 'BB_uniq_40'
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_icache.v(86,1-506,10) (VERI-9000) elaborating module 'lm32_icache_uniq_1'
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_dcache.v(80,1-551,10) (VERI-9000) elaborating module 'lm32_dcache_uniq_1'
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_addsub.v(55,1-114,10) (VERI-9000) elaborating module 'lm32_addsub_uniq_1'
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/typea.v(65,1-102,10) (VERI-9000) elaborating module 'TYPEA_uniq_1'
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/typea.v(65,1-102,10) (VERI-9000) elaborating module 'TYPEA_uniq_2'
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/typea.v(65,1-102,10) (VERI-9000) elaborating module 'TYPEA_uniq_3'
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/typea.v(65,1-102,10) (VERI-9000) elaborating module 'TYPEA_uniq_4'
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/typea.v(65,1-102,10) (VERI-9000) elaborating module 'TYPEA_uniq_5'
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/typea.v(65,1-102,10) (VERI-9000) elaborating module 'TYPEA_uniq_6'
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/typea.v(65,1-102,10) (VERI-9000) elaborating module 'TYPEA_uniq_7'
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/typea.v(65,1-102,10) (VERI-9000) elaborating module 'TYPEA_uniq_8'
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/typea.v(65,1-102,10) (VERI-9000) elaborating module 'TYPEA_uniq_9'
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/typea.v(65,1-102,10) (VERI-9000) elaborating module 'TYPEA_uniq_10'
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/typea.v(65,1-102,10) (VERI-9000) elaborating module 'TYPEA_uniq_11'
INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1291,1-1358,10) (VERI-9000) elaborating module 'DP8KC_uniq_1'
INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1291,1-1358,10) (VERI-9000) elaborating module 'DP8KC_uniq_2'
INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1291,1-1358,10) (VERI-9000) elaborating module 'DP8KC_uniq_3'
INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1291,1-1358,10) (VERI-9000) elaborating module 'DP8KC_uniq_4'
INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1120,1-1122,10) (VERI-9000) elaborating module 'VHI_uniq_4'
INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1124,1-1126,10) (VERI-9000) elaborating module 'VLO_uniq_2'
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_ram.v(61,1-310,10) (VERI-9000) elaborating module 'lm32_ram_uniq_1'
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_ram.v(61,1-310,10) (VERI-9000) elaborating module 'lm32_ram_uniq_2'
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_ram.v(61,1-310,10) (VERI-9000) elaborating module 'lm32_ram_uniq_3'
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/lm32_ram.v(61,1-310,10) (VERI-9000) elaborating module 'lm32_ram_uniq_4'
INFO - C:/TFG/exp7/mic32/soc/mic32_vhd.vhd(48,1-64,6) (VHDL-1400) back to vhdl to continue elaboration
INFO - C:/TFG/exp7/proy_glob/proy_glob.v(38,1-38,67) (VERI-1232) back to verilog to continue elaboration
WARNING - C:/TFG/exp7/mic32/soc/mic32.v(612,1-645,35) (VERI-1927) port PIO_IN remains unconnected for this instance
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/typeb.v(51,8-51,13) (VERI-1018) compiling module TYPEB
INFO - C:/TFG/exp7/mic32/soc/../components/lm32_top/rtl/verilog/typeb.v(51,1-78,10) (VERI-9000) elaborating module 'TYPEB'
Done: design load finished with (0) errors, and (12) warnings