PAR: Place And Route Diamond Version 3.8.0.115.3. Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2016 Lattice Semiconductor Corporation, All rights reserved. Wed Sep 27 06:09:34 2017 C:/lscc/diamond/3.8/ispfpga\bin\nt\par -f proyecto_global_proyecto_global.p2t proyecto_global_proyecto_global_map.ncd proyecto_global_proyecto_global.dir proyecto_global_proyecto_global.prf -gui -msgset C:/TFG/exp6_2/promote.xml Preference file: proyecto_global_proyecto_global.prf. Cost Table Summary Level/ Number Worst Timing Worst Timing Run NCD Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status ---------- -------- ----- ------ ----------- ----------- ---- ------ 5_1 * 0 18.224 0 0.325 0 14 Complete * : Design saved. Total (real) run time for 1-seed: 14 secs par done! Lattice Place and Route Report for Design "proyecto_global_proyecto_global_map.ncd" Wed Sep 27 06:09:34 2017 Best Par Run PAR: Place And Route Diamond Version 3.8.0.115.3. Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset C:/TFG/exp6_2/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF proyecto_global_proyecto_global_map.ncd proyecto_global_proyecto_global.dir/5_1.ncd proyecto_global_proyecto_global.prf Preference file: proyecto_global_proyecto_global.prf. Placement level-cost: 5-1. Routing Iterations: 6 Loading design for application par from file proyecto_global_proyecto_global_map.ncd. Design name: esquema_global NCD version: 3.3 Vendor: LATTICE Device: LCMXO2-7000HE Package: TQFP144 Performance: 4 Loading device for application par from file 'xo2c7000.nph' in environment: C:/lscc/diamond/3.8/ispfpga. Package Status: Final Version 1.39. Performance Hardware Data Status: Final Version 34.4. License checked out. Ignore Preference Error(s): True Device utilization summary: PIO (prelim) 28+4(JTAG)/336 10% used 28+4(JTAG)/115 28% bonded IOLOGIC 2/336 <1% used SLICE 295/3432 8% used GSR 1/1 100% used OSC 1/1 100% used EBR 6/26 23% used PLL 1/2 50% used INFO: Design contains EBR with ASYNC Reset Mode that has a limitation: The use of the EBR block asynchronous reset requires that certain timing be met between the clock and the reset within the memory block. See the device specific data sheet for additional details. INFO: Design contains pre-loadable EBR during configuration that has a requirement: Since the GSR is disabled for the EBR, make sure write enable and chip enable are inactive during wake-up, so that the pre-loaded initialization values will not be corrupted during wake-up state. Number of Signals: 897 Number of Connections: 2625 Pin Constraint Summary: 28 out of 28 pins locked (100% locked). WARNING - par: PIO driver comp "clk_ext_sal" of PLL "I101/PLLInst_0" CLKI input will be placed on a non-dedicated PIO site "27/PL22A"; therefore, general routing has to be used. The following 4 signals are selected to use the primary clock routing resources: I101/CLKOP (driver: I101/PLLInst_0, clk load #: 0) N_43 (driver: I84/SLICE_1, clk load #: 117) sen_1mhz (driver: I101/PLLInst_0, clk load #: 13) N_48 (driver: I5, clk load #: 11) The following 4 signals are selected to use the secondary clock routing resources: Q[20] (driver: I7/SLICE_177, clk load #: 6, sr load #: 13, ce load #: 0) I82/lm8_inst/counter[2] (driver: I82/lm8_inst/SLICE_157, clk load #: 0, sr load #: 24, ce load #: 0) N_64 (driver: I101/PLLInst_0, clk load #: 6, sr load #: 0, ce load #: 0) N_45 (driver: aclr_a1hz, clk load #: 0, sr load #: 11, ce load #: 0) WARNING - par: Signal "N_45" is selected to use Secondary clock resources. However, its driver comp "aclr_a1hz" is located at "76", which is not a dedicated pin for connecting to Secondary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew. Signal I82/lm8_inst/LM8/rst_n is selected as Global Set/Reset. Starting Placer Phase 0. ........... Finished Placer Phase 0. REAL time: 2 secs Starting Placer Phase 1. .................... Placer score = 147476. Finished Placer Phase 1. REAL time: 8 secs Starting Placer Phase 2. . Placer score = 145922 Finished Placer Phase 2. REAL time: 8 secs Clock Report Global Clock Resources: CLK_PIN : 0 out of 8 (0%) General PIO: 1 out of 336 (0%) PLL : 1 out of 2 (50%) DCM : 0 out of 2 (0%) DCC : 0 out of 8 (0%) Quadrants All (TL, TR, BL, BR) - Global Clocks: PRIMARY "I101/CLKOP" from CLKOP on comp "I101/PLLInst_0" on PLL site "LPLL", clk load = 0 PRIMARY "N_43" from Q0 on comp "I84/SLICE_1" on site "R2C19B", clk load = 117 PRIMARY "sen_1mhz" from CLKOS2 on comp "I101/PLLInst_0" on PLL site "LPLL", clk load = 13 PRIMARY "N_48" from OSC on comp "I5" on site "OSC", clk load = 11 SECONDARY "Q[20]" from Q0 on comp "I7/SLICE_177" on site "R21C18B", clk load = 6, ce load = 0, sr load = 13 SECONDARY "I82/lm8_inst/counter[2]" from Q0 on comp "I82/lm8_inst/SLICE_157" on site "R21C20C", clk load = 0, ce load = 0, sr load = 24 SECONDARY "N_64" from CLKOS3 on comp "I101/PLLInst_0" on PLL site "LPLL", clk load = 6, ce load = 0, sr load = 0 SECONDARY "N_45" from comp "aclr_a1hz" on PIO site "76 (PR23A)", clk load = 0, ce load = 0, sr load = 11 PRIMARY : 4 out of 8 (50%) SECONDARY: 4 out of 8 (50%) Edge Clocks: No edge clock selected. I/O Usage Summary (final): 28 + 4(JTAG) out of 336 (9.5%) PIO sites used. 28 + 4(JTAG) out of 115 (27.8%) bonded PIO sites used. Number of PIO comps: 28; differential: 0. Number of Vref pins used: 0. I/O Bank Usage Summary: +----------+----------------+------------+-----------+ | I/O Bank | Usage | Bank Vccio | Bank Vref | +----------+----------------+------------+-----------+ | 0 | 0 / 28 ( 0%) | - | - | | 1 | 10 / 29 ( 34%) | 3.3V | - | | 2 | 0 / 29 ( 0%) | - | - | | 3 | 7 / 9 ( 77%) | 3.3V | - | | 4 | 6 / 10 ( 60%) | 3.3V | - | | 5 | 5 / 10 ( 50%) | 3.3V | - | +----------+----------------+------------+-----------+ Total placer CPU time: 8 secs Dumping design to file proyecto_global_proyecto_global.dir/5_1.ncd. 0 connections routed; 2625 unrouted. Starting router resource preassignment WARNING - par: Unable to route net (PIO to PLL_CLKI) with dedicated resource for net clk_ext_sal_c. WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew. Signal=clk_ext_sal_c loads=2 clock_loads=2 Completed router resource preassignment. Real time: 10 secs Start NBR router at 06:09:45 09/27/17 ***************************************************************** Info: NBR allows conflicts(one node used by more than one signal) in the earlier iterations. In each iteration, it tries to solve the conflicts while keeping the critical connections routed as short as possible. The routing process is said to be completed when no conflicts exist and all connections are routed. Note: NBR uses a different method to calculate timing slacks. The worst slack and total negative slack may not be the same as that in TRCE report. You should always run TRCE to verify your design. ***************************************************************** Start NBR special constraint process at 06:09:45 09/27/17 Start NBR section for initial routing at 06:09:45 09/27/17 Level 4, iteration 1 76(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack<setup>: 18.224ns/0.000ns; real time: 12 secs Info: Initial congestion level at 75% usage is 0 Info: Initial congestion area at 75% usage is 0 (0.00%) Start NBR section for normal routing at 06:09:46 09/27/17 Level 4, iteration 1 39(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack<setup>: 18.224ns/0.000ns; real time: 12 secs Level 4, iteration 2 19(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack<setup>: 18.224ns/0.000ns; real time: 12 secs Level 4, iteration 3 9(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack<setup>: 18.224ns/0.000ns; real time: 12 secs Level 4, iteration 4 1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack<setup>: 18.224ns/0.000ns; real time: 12 secs Level 4, iteration 5 0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack<setup>: 18.224ns/0.000ns; real time: 12 secs Start NBR section for setup/hold timing optimization with effort level 3 at 06:09:46 09/27/17 Start NBR section for re-routing at 06:09:46 09/27/17 Level 4, iteration 1 0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack<setup>: 18.224ns/0.000ns; real time: 12 secs Start NBR section for post-routing at 06:09:46 09/27/17 End NBR router with 0 unrouted connection NBR Summary ----------- Number of unrouted connections : 0 (0.00%) Number of connections with timing violations : 0 (0.00%) Estimated worst slack<setup> : 18.224ns Timing score<setup> : 0 ----------- Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored. WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew. Signal=clk_ext_sal_c loads=2 clock_loads=2 Total CPU time 13 secs Total REAL time: 13 secs Completely routed. End of route. 2625 routed (100.00%); 0 unrouted. Hold time timing score: 0, hold timing errors: 0 Timing score: 0 Dumping design to file proyecto_global_proyecto_global.dir/5_1.ncd. All signals are completely routed. PAR_SUMMARY::Run status = completed PAR_SUMMARY::Number of unrouted conns = 0 PAR_SUMMARY::Worst slack<setup/<ns>> = 18.224 PAR_SUMMARY::Timing score<setup/<ns>> = 0.000 PAR_SUMMARY::Worst slack<hold /<ns>> = 0.325 PAR_SUMMARY::Timing score<hold /<ns>> = 0.000 PAR_SUMMARY::Number of errors = 0 Total CPU time to completion: 13 secs Total REAL time to completion: 14 secs par done! Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2016 Lattice Semiconductor Corporation, All rights reserved.