Setting log file to 'C:/TFG/exp5/dis_micro5/hdla_gen_hierarchy.html'.
Starting: parse design source files
(VERI-1482) Analyzing Verilog file C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v
Done: design load finished with (0) errors, and (0) warnings