Project Settings
Project Name proj_1 Implementation Name proyecto_global
Top Module esquema_global Pipelining 1
Retiming 0 Resource Sharing 1
Fanout Guide 1000 Disable I/O Insertion 0
Disable Sequential Optimizations 0 Clock Conversion 1

Run Status
Job Name Status CPU Time Real Time Memory Date/Time
(compiler)Complete 82 449 0 - 0m:02s - 16/09/2017
3:39:51
(premap)Complete 2 4 0 0m:00s 0m:00s 145MB 16/09/2017
3:39:53
(fpga_mapper)Complete 120 25 0 0m:04s 0m:04s 184MB 16/09/2017
3:39:58
Multi-srs Generator Complete16/09/2017
3:39:52

Area Summary
Register bits 205 I/O cells 30
Block RAMs (v_ram) 0 DSPs (dsp_used) 0
ORCA LUTs (total_luts) 310

Timing Summary
Clock NameReq FreqEst FreqSlack
div2|tdataout0_derived_clock1.0 MHz112.5 MHz1982.227
divfrec1|tdataout20_derived_clock2.1 MHzNANA
esquema_global|N_44_inferred_clock1.0 MHz165.2 MHz993.946
esquema_global|N_45_inferred_clock2.1 MHz201.0 MHz475.795
esquema_global|clk_ext_sal1.0 MHz259.0 MHz996.139
pll1|CLKOS3_inferred_clock1.0 MHz343.8 MHz997.091
System1.0 MHz61.4 MHz983.707

Optimizations Summary
Combined Clock Conversion 3 / 3