#Build: Synplify Pro L-2016.03L-1, Build 097R, Jul  4 2016
#install: C:\lscc\diamond\3.8\synpbase
#OS: Windows 8 6.2
#Hostname: RORDRIGO

# Sat Sep 30 04:33:29 2017

#Implementation: esquema_con_gpio

Synopsys HDL Compiler, version comp2016q2rc, Build 192R, built Jul  5 2016
@N: :  | Running in 64-bit mode 
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.

Synopsys VHDL Compiler, version comp2016q2rc, Build 192R, built Jul  5 2016
@N: :  | Running in 64-bit mode 
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.

@N:CD720 : std.vhd(123) | Setting time resolution to ns
@N: : div2.vhd(14) | Top entity is set to div2.
VHDL syntax check successful!

At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)


Process completed successfully.
# Sat Sep 30 04:33:30 2017

###########################################################]
Synopsys Verilog Compiler, version comp2016q2rc, Build 192R, built Jul  5 2016
@N: :  | Running in 64-bit mode 
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.

@I::"C:\lscc\diamond\3.8\synpbase\lib\lucent\machxo2.v" (library work)
@I::"C:\lscc\diamond\3.8\synpbase\lib\lucent\pmi_def.v" (library work)
@I::"C:\lscc\diamond\3.8\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__)
@I::"C:\lscc\diamond\3.8\synpbase\lib\vlog\umr_capim.v" (library snps_haps)
@I::"C:\lscc\diamond\3.8\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
@I::"C:\lscc\diamond\3.8\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
@I::"C:\TFG\exp4\esquema_con_gpio\esquema_con_gpio.v" (library work)
@I::"C:\TFG\exp4\dos_gpio\soc\dos_gpio.v" (library work)
@I:"C:\TFG\exp4\dos_gpio\soc\dos_gpio.v":"C:\TFG\exp4\dos_gpio\soc\system_conf.v" (library work)
@I:"C:\TFG\exp4\dos_gpio\soc\dos_gpio.v":"C:\TFG\exp4\dos_gpio\soc\../components/lm8/rtl/verilog\lm8_include_all.v" (library work)
@I:"C:\TFG\exp4\dos_gpio\soc\../components/lm8/rtl/verilog\lm8_include_all.v":"C:\TFG\exp4\dos_gpio\soc\pmi_def.v" (library work)
@I:"C:\TFG\exp4\dos_gpio\soc\../components/lm8/rtl/verilog\lm8_include_all.v":"C:\TFG\exp4\dos_gpio\soc\../components/lm8/rtl/verilog\lm8_include.v" (library work)
@I:"C:\TFG\exp4\dos_gpio\soc\../components/lm8/rtl/verilog\lm8_include_all.v":"C:\TFG\exp4\dos_gpio\soc\../components/lm8/rtl/verilog\lm8_interrupt.v" (library work)
@I:"C:\TFG\exp4\dos_gpio\soc\../components/lm8/rtl/verilog\lm8_include_all.v":"C:\TFG\exp4\dos_gpio\soc\../components/lm8/rtl/verilog\lm8_io_cntl.v" (library work)
@I:"C:\TFG\exp4\dos_gpio\soc\../components/lm8/rtl/verilog\lm8_include_all.v":"C:\TFG\exp4\dos_gpio\soc\../components/lm8/rtl/verilog\lm8_flow_cntl.v" (library work)
@I:"C:\TFG\exp4\dos_gpio\soc\../components/lm8/rtl/verilog\lm8_include_all.v":"C:\TFG\exp4\dos_gpio\soc\../components/lm8/rtl/verilog\lm8_idec.v" (library work)
@I:"C:\TFG\exp4\dos_gpio\soc\../components/lm8/rtl/verilog\lm8_include_all.v":"C:\TFG\exp4\dos_gpio\soc\../components/lm8/rtl/verilog\lm8_alu.v" (library work)
@I:"C:\TFG\exp4\dos_gpio\soc\../components/lm8/rtl/verilog\lm8_include_all.v":"C:\TFG\exp4\dos_gpio\soc\../components/lm8/rtl/verilog\lm8_core.v" (library work)
@I:"C:\TFG\exp4\dos_gpio\soc\../components/lm8/rtl/verilog\lm8_include_all.v":"C:\TFG\exp4\dos_gpio\soc\../components/lm8/rtl/verilog\lm8_top.v" (library work)
@I:"C:\TFG\exp4\dos_gpio\soc\dos_gpio.v":"C:\TFG\exp4\dos_gpio\soc\../components/gpio/rtl/verilog\gpio.v" (library work)
@W:CG921 : gpio.v(252) | ipd_idx is already declared in this scope.
@W:CG921 : gpio.v(262) | jpd_idx is already declared in this scope.
@W:CG921 : gpio.v(273) | kpd_idx is already declared in this scope.
@W:CG921 : gpio.v(284) | lpd_idx is already declared in this scope.
@W:CG921 : gpio.v(390) | iopd_idx is already declared in this scope.
@W:CG921 : gpio.v(400) | jopd_idx is already declared in this scope.
@W:CG921 : gpio.v(411) | kopd_idx is already declared in this scope.
@W:CG921 : gpio.v(422) | lopd_idx is already declared in this scope.
@W:CG921 : gpio.v(432) | mopd_idx is already declared in this scope.
@W:CG921 : gpio.v(442) | nopd_idx is already declared in this scope.
@W:CG921 : gpio.v(453) | oopd_idx is already declared in this scope.
@W:CG921 : gpio.v(464) | popd_idx is already declared in this scope.
@W:CG921 : gpio.v(645) | iti is already declared in this scope.
@W:CG921 : gpio.v(672) | jti is already declared in this scope.
@W:CG921 : gpio.v(700) | kti is already declared in this scope.
@W:CG921 : gpio.v(728) | lti is already declared in this scope.
@W:CG921 : gpio.v(1112) | im_idx is already declared in this scope.
@W:CG921 : gpio.v(1122) | jm_idx is already declared in this scope.
@W:CG921 : gpio.v(1133) | km_idx is already declared in this scope.
@W:CG921 : gpio.v(1144) | lm_idx is already declared in this scope.
@W:CG921 : gpio.v(1155) | imb_idx is already declared in this scope.
@W:CG921 : gpio.v(1165) | jmb_idx is already declared in this scope.
@W:CG921 : gpio.v(1176) | kmb_idx is already declared in this scope.
@W:CG921 : gpio.v(1187) | lmb_idx is already declared in this scope.
@W:CG921 : gpio.v(1270) | i is already declared in this scope.
@W:CG921 : gpio.v(1282) | j is already declared in this scope.
@W:CG921 : gpio.v(1295) | k is already declared in this scope.
@W:CG921 : gpio.v(1308) | l is already declared in this scope.
@W:CG921 : gpio.v(1339) | i is already declared in this scope.
@W:CG921 : gpio.v(1363) | j is already declared in this scope.
@W:CG921 : gpio.v(1388) | k is already declared in this scope.
@W:CG921 : gpio.v(1413) | l is already declared in this scope.
@W:CG921 : gpio.v(1440) | i is already declared in this scope.
@W:CG921 : gpio.v(1464) | j is already declared in this scope.
@W:CG921 : gpio.v(1489) | k is already declared in this scope.
@W:CG921 : gpio.v(1514) | l is already declared in this scope.
@W:CG921 : gpio.v(1606) | iitb_idx is already declared in this scope.
@W:CG921 : gpio.v(1618) | jitb_idx is already declared in this scope.
@W:CG921 : gpio.v(1631) | kitb_idx is already declared in this scope.
@W:CG921 : gpio.v(1644) | litb_idx is already declared in this scope.
@W:CG921 : gpio.v(1773) | i_both is already declared in this scope.
@W:CG921 : gpio.v(1796) | j_both is already declared in this scope.
@W:CG921 : gpio.v(1820) | k_both is already declared in this scope.
@W:CG921 : gpio.v(1844) | l_both is already declared in this scope.
@I:"C:\TFG\exp4\dos_gpio\soc\dos_gpio.v":"C:\TFG\exp4\dos_gpio\soc\../components/gpio/rtl/verilog\tpio.v" (library work)
Verilog syntax check successful!

At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 73MB peak: 74MB)


Process completed successfully.
# Sat Sep 30 04:33:30 2017

###########################################################]
@I::"C:\lscc\diamond\3.8\synpbase\lib\lucent\machxo2.v" (library work)
@I::"C:\lscc\diamond\3.8\synpbase\lib\lucent\pmi_def.v" (library work)
@I::"C:\lscc\diamond\3.8\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__)
@I::"C:\lscc\diamond\3.8\synpbase\lib\vlog\umr_capim.v" (library snps_haps)
@I::"C:\lscc\diamond\3.8\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
@I::"C:\lscc\diamond\3.8\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
@I::"C:\TFG\exp4\esquema_con_gpio\esquema_con_gpio.v" (library work)
@I::"C:\TFG\exp4\dos_gpio\soc\dos_gpio.v" (library work)
@I:"C:\TFG\exp4\dos_gpio\soc\dos_gpio.v":"C:\TFG\exp4\dos_gpio\soc\system_conf.v" (library work)
@I:"C:\TFG\exp4\dos_gpio\soc\dos_gpio.v":"C:\TFG\exp4\dos_gpio\soc\../components/lm8/rtl/verilog\lm8_include_all.v" (library work)
@I:"C:\TFG\exp4\dos_gpio\soc\../components/lm8/rtl/verilog\lm8_include_all.v":"C:\TFG\exp4\dos_gpio\soc\pmi_def.v" (library work)
@I:"C:\TFG\exp4\dos_gpio\soc\../components/lm8/rtl/verilog\lm8_include_all.v":"C:\TFG\exp4\dos_gpio\soc\../components/lm8/rtl/verilog\lm8_include.v" (library work)
@I:"C:\TFG\exp4\dos_gpio\soc\../components/lm8/rtl/verilog\lm8_include_all.v":"C:\TFG\exp4\dos_gpio\soc\../components/lm8/rtl/verilog\lm8_interrupt.v" (library work)
@I:"C:\TFG\exp4\dos_gpio\soc\../components/lm8/rtl/verilog\lm8_include_all.v":"C:\TFG\exp4\dos_gpio\soc\../components/lm8/rtl/verilog\lm8_io_cntl.v" (library work)
@I:"C:\TFG\exp4\dos_gpio\soc\../components/lm8/rtl/verilog\lm8_include_all.v":"C:\TFG\exp4\dos_gpio\soc\../components/lm8/rtl/verilog\lm8_flow_cntl.v" (library work)
@I:"C:\TFG\exp4\dos_gpio\soc\../components/lm8/rtl/verilog\lm8_include_all.v":"C:\TFG\exp4\dos_gpio\soc\../components/lm8/rtl/verilog\lm8_idec.v" (library work)
@I:"C:\TFG\exp4\dos_gpio\soc\../components/lm8/rtl/verilog\lm8_include_all.v":"C:\TFG\exp4\dos_gpio\soc\../components/lm8/rtl/verilog\lm8_alu.v" (library work)
@I:"C:\TFG\exp4\dos_gpio\soc\../components/lm8/rtl/verilog\lm8_include_all.v":"C:\TFG\exp4\dos_gpio\soc\../components/lm8/rtl/verilog\lm8_core.v" (library work)
@I:"C:\TFG\exp4\dos_gpio\soc\../components/lm8/rtl/verilog\lm8_include_all.v":"C:\TFG\exp4\dos_gpio\soc\../components/lm8/rtl/verilog\lm8_top.v" (library work)
@I:"C:\TFG\exp4\dos_gpio\soc\dos_gpio.v":"C:\TFG\exp4\dos_gpio\soc\../components/gpio/rtl/verilog\gpio.v" (library work)
@W:CG921 : gpio.v(252) | ipd_idx is already declared in this scope.
@W:CG921 : gpio.v(262) | jpd_idx is already declared in this scope.
@W:CG921 : gpio.v(273) | kpd_idx is already declared in this scope.
@W:CG921 : gpio.v(284) | lpd_idx is already declared in this scope.
@W:CG921 : gpio.v(390) | iopd_idx is already declared in this scope.
@W:CG921 : gpio.v(400) | jopd_idx is already declared in this scope.
@W:CG921 : gpio.v(411) | kopd_idx is already declared in this scope.
@W:CG921 : gpio.v(422) | lopd_idx is already declared in this scope.
@W:CG921 : gpio.v(432) | mopd_idx is already declared in this scope.
@W:CG921 : gpio.v(442) | nopd_idx is already declared in this scope.
@W:CG921 : gpio.v(453) | oopd_idx is already declared in this scope.
@W:CG921 : gpio.v(464) | popd_idx is already declared in this scope.
@W:CG921 : gpio.v(645) | iti is already declared in this scope.
@W:CG921 : gpio.v(672) | jti is already declared in this scope.
@W:CG921 : gpio.v(700) | kti is already declared in this scope.
@W:CG921 : gpio.v(728) | lti is already declared in this scope.
@W:CG921 : gpio.v(1112) | im_idx is already declared in this scope.
@W:CG921 : gpio.v(1122) | jm_idx is already declared in this scope.
@W:CG921 : gpio.v(1133) | km_idx is already declared in this scope.
@W:CG921 : gpio.v(1144) | lm_idx is already declared in this scope.
@W:CG921 : gpio.v(1155) | imb_idx is already declared in this scope.
@W:CG921 : gpio.v(1165) | jmb_idx is already declared in this scope.
@W:CG921 : gpio.v(1176) | kmb_idx is already declared in this scope.
@W:CG921 : gpio.v(1187) | lmb_idx is already declared in this scope.
@W:CG921 : gpio.v(1270) | i is already declared in this scope.
@W:CG921 : gpio.v(1282) | j is already declared in this scope.
@W:CG921 : gpio.v(1295) | k is already declared in this scope.
@W:CG921 : gpio.v(1308) | l is already declared in this scope.
@W:CG921 : gpio.v(1339) | i is already declared in this scope.
@W:CG921 : gpio.v(1363) | j is already declared in this scope.
@W:CG921 : gpio.v(1388) | k is already declared in this scope.
@W:CG921 : gpio.v(1413) | l is already declared in this scope.
@W:CG921 : gpio.v(1440) | i is already declared in this scope.
@W:CG921 : gpio.v(1464) | j is already declared in this scope.
@W:CG921 : gpio.v(1489) | k is already declared in this scope.
@W:CG921 : gpio.v(1514) | l is already declared in this scope.
@W:CG921 : gpio.v(1606) | iitb_idx is already declared in this scope.
@W:CG921 : gpio.v(1618) | jitb_idx is already declared in this scope.
@W:CG921 : gpio.v(1631) | kitb_idx is already declared in this scope.
@W:CG921 : gpio.v(1644) | litb_idx is already declared in this scope.
@W:CG921 : gpio.v(1773) | i_both is already declared in this scope.
@W:CG921 : gpio.v(1796) | j_both is already declared in this scope.
@W:CG921 : gpio.v(1820) | k_both is already declared in this scope.
@W:CG921 : gpio.v(1844) | l_both is already declared in this scope.
@I:"C:\TFG\exp4\dos_gpio\soc\dos_gpio.v":"C:\TFG\exp4\dos_gpio\soc\../components/gpio/rtl/verilog\tpio.v" (library work)
Verilog syntax check successful!
File C:\TFG\exp4\esquema_con_gpio\esquema_con_gpio.v changed - recompiling
@N:CG364 : machxo2.v(563) | Synthesizing module INV in library work.

@N:CG364 : machxo2.v(857) | Synthesizing module OB in library work.

@N:CG364 : machxo2.v(498) | Synthesizing module IB in library work.

@N:CG364 : machxo2.v(1120) | Synthesizing module VHI in library work.

@N:CG364 : esquema_con_gpio.v(3) | Synthesizing module esquema_con_gpio in library work.

@N:CG794 : esquema_con_gpio.v(50) | Using module div2 from library work
@W:CG781 : esquema_con_gpio.v(50) | Input Aclr on instance I25 is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@N:CG794 : esquema_con_gpio.v(72) | Using module dos_gpio_vhd from library work

At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 73MB peak: 74MB)


Process completed successfully.
# Sat Sep 30 04:33:30 2017

###########################################################]
@N:CD720 : std.vhd(123) | Setting time resolution to ns
@N: : div2.vhd(14) | Top entity is set to div2.

File Dependency file is up to date.  It will not be rewritten.

VHDL syntax check successful!
@N:CD630 : dos_gpio_vhd.vhd(4) | Synthesizing work.dos_gpio_vhd.dos_gpio_vhd_a.
Post processing for work.dos_gpio_vhd.dos_gpio_vhd_a
@N:CD630 : div2.vhd(14) | Synthesizing work.div2.structure.
Post processing for work.div2.structure

At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 69MB peak: 69MB)


Process completed successfully.
# Sat Sep 30 04:33:30 2017

###########################################################]
@I::"C:\lscc\diamond\3.8\synpbase\lib\lucent\machxo2.v" (library work)
@I::"C:\lscc\diamond\3.8\synpbase\lib\lucent\pmi_def.v" (library work)
@I::"C:\lscc\diamond\3.8\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__)
@I::"C:\lscc\diamond\3.8\synpbase\lib\vlog\umr_capim.v" (library snps_haps)
@I::"C:\lscc\diamond\3.8\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
@I::"C:\lscc\diamond\3.8\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
@I::"C:\TFG\exp4\esquema_con_gpio\esquema_con_gpio.v" (library work)
@I::"C:\TFG\exp4\dos_gpio\soc\dos_gpio.v" (library work)
@I:"C:\TFG\exp4\dos_gpio\soc\dos_gpio.v":"C:\TFG\exp4\dos_gpio\soc\system_conf.v" (library work)
@I:"C:\TFG\exp4\dos_gpio\soc\dos_gpio.v":"C:\TFG\exp4\dos_gpio\soc\../components/lm8/rtl/verilog\lm8_include_all.v" (library work)
@I:"C:\TFG\exp4\dos_gpio\soc\../components/lm8/rtl/verilog\lm8_include_all.v":"C:\TFG\exp4\dos_gpio\soc\pmi_def.v" (library work)
@I:"C:\TFG\exp4\dos_gpio\soc\../components/lm8/rtl/verilog\lm8_include_all.v":"C:\TFG\exp4\dos_gpio\soc\../components/lm8/rtl/verilog\lm8_include.v" (library work)
@I:"C:\TFG\exp4\dos_gpio\soc\../components/lm8/rtl/verilog\lm8_include_all.v":"C:\TFG\exp4\dos_gpio\soc\../components/lm8/rtl/verilog\lm8_interrupt.v" (library work)
@I:"C:\TFG\exp4\dos_gpio\soc\../components/lm8/rtl/verilog\lm8_include_all.v":"C:\TFG\exp4\dos_gpio\soc\../components/lm8/rtl/verilog\lm8_io_cntl.v" (library work)
@I:"C:\TFG\exp4\dos_gpio\soc\../components/lm8/rtl/verilog\lm8_include_all.v":"C:\TFG\exp4\dos_gpio\soc\../components/lm8/rtl/verilog\lm8_flow_cntl.v" (library work)
@I:"C:\TFG\exp4\dos_gpio\soc\../components/lm8/rtl/verilog\lm8_include_all.v":"C:\TFG\exp4\dos_gpio\soc\../components/lm8/rtl/verilog\lm8_idec.v" (library work)
@I:"C:\TFG\exp4\dos_gpio\soc\../components/lm8/rtl/verilog\lm8_include_all.v":"C:\TFG\exp4\dos_gpio\soc\../components/lm8/rtl/verilog\lm8_alu.v" (library work)
@I:"C:\TFG\exp4\dos_gpio\soc\../components/lm8/rtl/verilog\lm8_include_all.v":"C:\TFG\exp4\dos_gpio\soc\../components/lm8/rtl/verilog\lm8_core.v" (library work)
@I:"C:\TFG\exp4\dos_gpio\soc\../components/lm8/rtl/verilog\lm8_include_all.v":"C:\TFG\exp4\dos_gpio\soc\../components/lm8/rtl/verilog\lm8_top.v" (library work)
@I:"C:\TFG\exp4\dos_gpio\soc\dos_gpio.v":"C:\TFG\exp4\dos_gpio\soc\../components/gpio/rtl/verilog\gpio.v" (library work)
@W:CG921 : gpio.v(252) | ipd_idx is already declared in this scope.
@W:CG921 : gpio.v(262) | jpd_idx is already declared in this scope.
@W:CG921 : gpio.v(273) | kpd_idx is already declared in this scope.
@W:CG921 : gpio.v(284) | lpd_idx is already declared in this scope.
@W:CG921 : gpio.v(390) | iopd_idx is already declared in this scope.
@W:CG921 : gpio.v(400) | jopd_idx is already declared in this scope.
@W:CG921 : gpio.v(411) | kopd_idx is already declared in this scope.
@W:CG921 : gpio.v(422) | lopd_idx is already declared in this scope.
@W:CG921 : gpio.v(432) | mopd_idx is already declared in this scope.
@W:CG921 : gpio.v(442) | nopd_idx is already declared in this scope.
@W:CG921 : gpio.v(453) | oopd_idx is already declared in this scope.
@W:CG921 : gpio.v(464) | popd_idx is already declared in this scope.
@W:CG921 : gpio.v(645) | iti is already declared in this scope.
@W:CG921 : gpio.v(672) | jti is already declared in this scope.
@W:CG921 : gpio.v(700) | kti is already declared in this scope.
@W:CG921 : gpio.v(728) | lti is already declared in this scope.
@W:CG921 : gpio.v(1112) | im_idx is already declared in this scope.
@W:CG921 : gpio.v(1122) | jm_idx is already declared in this scope.
@W:CG921 : gpio.v(1133) | km_idx is already declared in this scope.
@W:CG921 : gpio.v(1144) | lm_idx is already declared in this scope.
@W:CG921 : gpio.v(1155) | imb_idx is already declared in this scope.
@W:CG921 : gpio.v(1165) | jmb_idx is already declared in this scope.
@W:CG921 : gpio.v(1176) | kmb_idx is already declared in this scope.
@W:CG921 : gpio.v(1187) | lmb_idx is already declared in this scope.
@W:CG921 : gpio.v(1270) | i is already declared in this scope.
@W:CG921 : gpio.v(1282) | j is already declared in this scope.
@W:CG921 : gpio.v(1295) | k is already declared in this scope.
@W:CG921 : gpio.v(1308) | l is already declared in this scope.
@W:CG921 : gpio.v(1339) | i is already declared in this scope.
@W:CG921 : gpio.v(1363) | j is already declared in this scope.
@W:CG921 : gpio.v(1388) | k is already declared in this scope.
@W:CG921 : gpio.v(1413) | l is already declared in this scope.
@W:CG921 : gpio.v(1440) | i is already declared in this scope.
@W:CG921 : gpio.v(1464) | j is already declared in this scope.
@W:CG921 : gpio.v(1489) | k is already declared in this scope.
@W:CG921 : gpio.v(1514) | l is already declared in this scope.
@W:CG921 : gpio.v(1606) | iitb_idx is already declared in this scope.
@W:CG921 : gpio.v(1618) | jitb_idx is already declared in this scope.
@W:CG921 : gpio.v(1631) | kitb_idx is already declared in this scope.
@W:CG921 : gpio.v(1644) | litb_idx is already declared in this scope.
@W:CG921 : gpio.v(1773) | i_both is already declared in this scope.
@W:CG921 : gpio.v(1796) | j_both is already declared in this scope.
@W:CG921 : gpio.v(1820) | k_both is already declared in this scope.
@W:CG921 : gpio.v(1844) | l_both is already declared in this scope.
@I:"C:\TFG\exp4\dos_gpio\soc\dos_gpio.v":"C:\TFG\exp4\dos_gpio\soc\../components/gpio/rtl/verilog\tpio.v" (library work)
Verilog syntax check successful!
@N:CG364 : dos_gpio.v(48) | Synthesizing module arbiter2 in library work.

	MAX_DAT_WIDTH=32'b00000000000000000000000000001000
	WBS_DAT_WIDTH=32'b00000000000000000000000000001000
	WBM0_DAT_WIDTH=32'b00000000000000000000000000001000
	WBM1_DAT_WIDTH=32'b00000000000000000000000000001000
   Generated name = arbiter2_8s_8s_8s_8s

@N:CG364 : lm8_idec.v(47) | Synthesizing module lm8_idec in library work.

	PROM_AW=32'b00000000000000000000000000001011
   Generated name = lm8_idec_11s

@N:CG364 : pmi_def.v(69) | Synthesizing module pmi_addsub in library work.

	pmi_data_width=32'b00000000000000000000000000001000
	pmi_result_width=32'b00000000000000000000000000001000
	pmi_sign=24'b011011110110011001100110
	pmi_family=16'b0100010101000011
	module_type=80'b01110000011011010110100101011111011000010110010001100100011100110111010101100010
   Generated name = pmi_addsub_8s_8s_off_EC_pmi_addsub

@N:CG364 : lm8_alu.v(47) | Synthesizing module lm8_alu in library work.

	FAMILY_NAME=16'b0100010101000011
   Generated name = lm8_alu_EC

@N:CG364 : lm8_flow_cntl.v(49) | Synthesizing module lm8_flow_cntl in library work.

	PGM_STACK_AW=32'b00000000000000000000000000000100
	PGM_STACK_AD=32'b00000000000000000000000000010000
	STK_EBR=32'b00000000000000000000000000000000
	PROM_WB=32'b00000000000000000000000000000000
	PROM_AW=32'b00000000000000000000000000001011
	FAMILY_NAME=16'b0100010101000011
   Generated name = lm8_flow_cntl_4s_16s_0s_0s_11s_EC

@W:CG296 : lm8_flow_cntl.v(226) | Incomplete sensitivity list - assuming completeness
@W:CG290 : lm8_flow_cntl.v(235) | Referenced variable import_ is not in sensitivity list
@W:CG290 : lm8_flow_cntl.v(235) | Referenced variable export_ is not in sensitivity list
@N:CG364 : pmi_def.v(48) | Synthesizing module pmi_distributed_spram in library work.

	pmi_addr_depth=32'b00000000000000000000000000010000
	pmi_addr_width=32'b00000000000000000000000000000100
	pmi_data_width=32'b00000000000000000000000000001101
	pmi_regmode=40'b0110111001101111011100100110010101100111
	pmi_init_file=32'b01101110011011110110111001100101
	pmi_init_file_format=48'b011000100110100101101110011000010111001001111001
	pmi_family=16'b0100010101000011
	module_type=168'b011100000110110101101001010111110110010001101001011100110111010001110010011010010110001001110101011101000110010101100100010111110111001101110000011100100110000101101101
   Generated name = pmi_distributed_spram_16s_4s_13s_noreg_none_binary_EC_pmi_distributed_spram_1_layer2

@W:CG133 : lm8_flow_cntl.v(122) | Object fetch_cyc is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : lm8_flow_cntl.v(123) | Object fetch_cyc_nxt is declared but not assigned. Either assign a value or remove the declaration.
@N:CG364 : lm8_io_cntl.v(47) | Synthesizing module lm8_io_cntl in library work.

@N:CG364 : lm8_interrupt.v(49) | Synthesizing module lm8_interrupt in library work.

	INTERRUPTS=32'b00000000000000000000000000001000
   Generated name = lm8_interrupt_8s

@N:CG364 : lm8_core.v(47) | Synthesizing module lm8_core in library work.

	FAMILY_NAME=16'b0100010101000011
	EXT_AW=32'b00000000000000000000000000010000
	PROM_WB=32'b00000000000000000000000000000000
	PROM_AW=32'b00000000000000000000000000001011
	PROM_AD=32'b00000000000000000000100000000000
	REGISTERS_16=32'b00000000000000000000000000000000
	REGISTER_EBR=32'b00000000000000000000000000000000
	PGM_STACK_AW=32'b00000000000000000000000000000100
	PGM_STACK_AD=32'b00000000000000000000000000010000
	INTERRUPTS=32'b00000000000000000000000000001000
	REG13=5'b01101
	REG14=5'b01110
	REG15=5'b01111
   Generated name = lm8_core_Z2_layer2

@N:CG179 : lm8_core.v(352) | Removing redundant assignment.
@N:CG364 : pmi_def.v(24) | Synthesizing module pmi_distributed_dpram in library work.

	pmi_addr_depth=32'b00000000000000000000000000100000
	pmi_addr_width=32'b00000000000000000000000000000101
	pmi_data_width=32'b00000000000000000000000000001000
	pmi_regmode=40'b0110111001101111011100100110010101100111
	pmi_init_file=32'b01101110011011110110111001100101
	pmi_init_file_format=48'b011000100110100101101110011000010111001001111001
	pmi_family=16'b0100010101000011
	module_type=168'b011100000110110101101001010111110110010001101001011100110111010001110010011010010110001001110101011101000110010101100100010111110110010001110000011100100110000101101101
   Generated name = pmi_distributed_dpram_32s_5s_8s_noreg_none_binary_EC_pmi_distributed_dpram_3_layer2

@W:CG133 : lm8_core.v(115) | Object page_ptr2 is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : lm8_core.v(115) | Object page_ptr3 is declared but not assigned. Either assign a value or remove the declaration.
@N:CG364 : lm8_top.v(50) | Synthesizing module lm8 in library work.

	LATTICE_FAMILY=16'b0100010101000011
	CFG_ROM_EN=32'b00000000000000000000000000000000
	CFG_ROM_BASE_ADDRESS=32'b00000000000000000000000000000000
	I_CFG_XIP=32'b00000000000000000000000000000000
	CFG_PROM_INIT_FILE=312'b010000110011101000101111010101000100011001000111001011110110010101111000011100000011010000101111011001000110111101110011010111110110011101110000011010010110111100101111011000110110111101100100001100110010111101110000011100100110111101101101010111110110100101101110011010010111010000101110011011010110010101101101
	CFG_PROM_INIT_FILE_FORMAT=24'b011010000110010101111000
	CFG_PROM_SIZE=32'b00000000000000000000100000000000
	CFG_PROM_BASE_ADDRESS=32'b00000000000000000000000000000000
	CFG_SP_INIT_FILE=360'b010000110011101000101111010101000100011001000111001011110110010101111000011100000011010000101111011001000110111101110011010111110110011101110000011010010110111100101111011000110110111101100100001100110010111101110011011000110111001001100001011101000110001101101000011100000110000101100100010111110110100101101110011010010111010000101110011011010110010101101101
	CFG_SP_INIT_FILE_FORMAT=24'b011010000110010101111000
	SP_PORT_ENABLE=32'b00000000000000000000000000000001
	SP_SIZE=32'b00000000000000000000100000000000
	SP_BASE_ADDRESS=32'b00000000000000000000000000000000
	CFG_IO_BASE_ADDRESS=32'b10000000000000000000000000000000
	CFG_EXT_SIZE_8=32'b00000000000000000000000000000000
	CFG_EXT_SIZE_16=32'b00000000000000000000000000000001
	CFG_EXT_SIZE_32=32'b00000000000000000000000000000000
	CFG_REGISTER_16=32'b00000000000000000000000000000000
	CFG_REGISTER_32=32'b00000000000000000000000000000001
	CFG_EBR=32'b00000000000000000000000000000000
	CFG_DISTRIBUTED_RAM=32'b00000000000000000000000000000001
	CFG_CALL_STACK_8=32'b00000000000000000000000000000000
	CFG_CALL_STACK_16=32'b00000000000000000000000000000001
	CFG_CALL_STACK_32=32'b00000000000000000000000000000000
	INTERRUPTS=32'b00000000000000000000000000001000
	CFG_EXT_SIZE=32'b00000000000000000000000000010000
	CFG_CALL_STACK=32'b00000000000000000000000000010000
	PROM_AW=32'b00000000000000000000000000001011
	ALIGN_PROM_ROM_BASE=32'b00000000000000000000000000000000
	SP_AW=32'b00000000000000000000000000001011
	ALIGN_SP_BASE=32'b00000000000000000000000000000000
	ALIGN_SP_ROM_BASE=32'b00000000000000000001100000000000
	ALIGN_IO_BASE=32'b10000000000000000000000000000000
	PGM_STACK_AW=32'b00000000000000000000000000000100
	INTERNAL_SP_CHECK=32'b00000000000000000000000000000000
   Generated name = lm8_Z4_layer2

@N:CG364 : pmi_def.v(115) | Synthesizing module pmi_ram_dq in library work.

	pmi_addr_depth=32'b00000000000000000000100000000000
	pmi_addr_width=32'b00000000000000000000000000001011
	pmi_data_width=32'b00000000000000000000000000010010
	pmi_regmode=40'b0110111001101111011100100110010101100111
	pmi_gsr=56'b01100100011010010111001101100001011000100110110001100101
	pmi_resetmode=40'b0110000101110011011110010110111001100011
	pmi_optimization=40'b0111001101110000011001010110010101100100
	pmi_init_file=312'b010000110011101000101111010101000100011001000111001011110110010101111000011100000011010000101111011001000110111101110011010111110110011101110000011010010110111100101111011000110110111101100100001100110010111101110000011100100110111101101101010111110110100101101110011010010111010000101110011011010110010101101101
	pmi_init_file_format=24'b011010000110010101111000
	pmi_write_mode=48'b011011100110111101110010011011010110000101101100
	pmi_family=16'b0100010101000011
	module_type=80'b01110000011011010110100101011111011100100110000101101101010111110110010001110001
   Generated name = pmi_ram_dq_Z5_layer2

@W:CG133 : lm8_top.v(363) | Object first_fetch_nxt is declared but not assigned. Either assign a value or remove the declaration.
@N:CG364 : pmi_def.v(115) | Synthesizing module pmi_ram_dq in library work.

	pmi_addr_depth=32'b00000000000000000000100000000000
	pmi_addr_width=32'b00000000000000000000000000001011
	pmi_data_width=32'b00000000000000000000000000001000
	pmi_regmode=40'b0110111001101111011100100110010101100111
	pmi_gsr=56'b01100100011010010111001101100001011000100110110001100101
	pmi_resetmode=40'b0110000101110011011110010110111001100011
	pmi_optimization=40'b0111001101110000011001010110010101100100
	pmi_init_file=360'b010000110011101000101111010101000100011001000111001011110110010101111000011100000011010000101111011001000110111101110011010111110110011101110000011010010110111100101111011000110110111101100100001100110010111101110011011000110111001001100001011101000110001101101000011100000110000101100100010111110110100101101110011010010111010000101110011011010110010101101101
	pmi_init_file_format=24'b011010000110010101111000
	pmi_write_mode=48'b011011100110111101110010011011010110000101101100
	pmi_family=16'b0100010101000011
	module_type=80'b01110000011011010110100101011111011100100110000101101101010111110110010001110001
   Generated name = pmi_ram_dq_Z6_layer2

@W:CG133 : lm8_top.v(86) | Object I_CYC_O is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : lm8_top.v(87) | Object I_STB_O is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : lm8_top.v(88) | Object I_CTI_O is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : lm8_top.v(89) | Object I_BTE_O is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : lm8_top.v(90) | Object I_WE_O is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : lm8_top.v(91) | Object I_SEL_O is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : lm8_top.v(92) | Object I_DAT_O is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : lm8_top.v(93) | Object I_ADR_O is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : lm8_top.v(94) | Object I_LOCK_O is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : lm8_top.v(211) | Object prom_waddr is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : lm8_top.v(211) | Object prom_raddr is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : lm8_top.v(212) | Object prom_wdata is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : lm8_top.v(214) | Object sp_waddr is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : lm8_top.v(214) | Object sp_raddr is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : lm8_top.v(215) | Object sp_wdata is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : lm8_top.v(226) | Object prom_wb_addr is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : lm8_top.v(226) | Object prom_wb_addr_nxt is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : lm8_top.v(227) | Object prom_wb_instr is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : lm8_top.v(227) | Object prom_wb_instr_nxt is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : lm8_top.v(228) | Object prom_wb_state is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : lm8_top.v(228) | Object prom_wb_state_nxt is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : lm8_top.v(412) | Object ext_din is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : lm8_top.v(414) | Object sp_rd_addr is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : lm8_top.v(414) | Object sp_rd_addr_nxt is declared but not assigned. Either assign a value or remove the declaration.
@W:CG360 : lm8_top.v(643) | Removing wire core_start, as there is no assignment to it.
@W:CG133 : lm8_top.v(644) | Object prom_copy_done is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : lm8_top.v(644) | Object prom_copy_done_nxt is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : lm8_top.v(645) | Object sp_copy_done is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : lm8_top.v(645) | Object sp_copy_done_nxt is declared but not assigned. Either assign a value or remove the declaration.
@N:CG364 : gpio.v(80) | Synthesizing module gpio in library work.

	GPIO_WB_DAT_WIDTH=32'b00000000000000000000000000001000
	GPIO_WB_ADR_WIDTH=32'b00000000000000000000000000000100
	DATA_WIDTH=32'b00000000000000000000000000001000
	INPUT_WIDTH=32'b00000000000000000000000000000001
	OUTPUT_WIDTH=32'b00000000000000000000000000000001
	IRQ_MODE=32'b00000000000000000000000000000000
	LEVEL=32'b00000000000000000000000000000000
	EDGE=32'b00000000000000000000000000000001
	POSE_EDGE_IRQ=32'b00000000000000000000000000000001
	NEGE_EDGE_IRQ=32'b00000000000000000000000000000000
	EITHER_EDGE_IRQ=32'b00000000000000000000000000000000
	INPUT_PORTS_ONLY=32'b00000000000000000000000000000001
	OUTPUT_PORTS_ONLY=32'b00000000000000000000000000000000
	BOTH_INPUT_AND_OUTPUT=32'b00000000000000000000000000000000
	TRISTATE_PORTS=32'b00000000000000000000000000000000
	UDLY=32'b00000000000000000000000000000001
   Generated name = gpio_Z7_layer2

@N:CG364 : machxo2.v(82) | Synthesizing module BB in library work.

@N:CG364 : tpio.v(66) | Synthesizing module tpio in library work.

	DATA_WIDTH=32'b00000000000000000000000000000001
	IRQ_MODE=32'b00000000000000000000000000000000
	LEVEL=32'b00000000000000000000000000000000
	EDGE=32'b00000000000000000000000000000001
	POSE_EDGE_IRQ=32'b00000000000000000000000000000001
	NEGE_EDGE_IRQ=32'b00000000000000000000000000000000
	EITHER_EDGE_IRQ=32'b00000000000000000000000000000000
	UDLY=32'b00000000000000000000000000000001
   Generated name = tpio_1s_0s_0s_1s_1s_0s_0s_1s

@W:CG133 : tpio.v(109) | Object IRQ_MASK is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : tpio.v(110) | Object IRQ_TEMP is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : tpio.v(111) | Object EDGE_CAPTURE is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : tpio.v(112) | Object PIO_DATA_DLY is declared but not assigned. Either assign a value or remove the declaration.
@W:CG360 : gpio.v(123) | Removing wire PIO_OUT, as there is no assignment to it.
@W:CG360 : gpio.v(124) | Removing wire PIO_BOTH_OUT, as there is no assignment to it.
@W:CG133 : gpio.v(145) | Object PIO_DATAO is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : gpio.v(146) | Object PIO_DATAI is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : gpio.v(167) | Object IRQ_MASK is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : gpio.v(168) | Object IRQ_MASK_BOTH is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : gpio.v(169) | Object IRQ_TEMP is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : gpio.v(170) | Object IRQ_TEMP_BOTH is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : gpio.v(171) | Object EDGE_CAPTURE is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : gpio.v(172) | Object EDGE_CAPTURE_BOTH is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : gpio.v(173) | Object PIO_DATA_DLY is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : gpio.v(174) | Object PIO_DATA_DLY_BOTH is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : gpio.v(252) | Object ipd_idx is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : gpio.v(262) | Object jpd_idx is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : gpio.v(273) | Object kpd_idx is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : gpio.v(284) | Object lpd_idx is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : gpio.v(390) | Object iopd_idx is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : gpio.v(400) | Object jopd_idx is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : gpio.v(411) | Object kopd_idx is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : gpio.v(422) | Object lopd_idx is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : gpio.v(432) | Object mopd_idx is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : gpio.v(442) | Object nopd_idx is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : gpio.v(453) | Object oopd_idx is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : gpio.v(464) | Object popd_idx is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : gpio.v(672) | Object jti is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : gpio.v(700) | Object kti is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : gpio.v(728) | Object lti is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : gpio.v(1112) | Object im_idx is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : gpio.v(1122) | Object jm_idx is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : gpio.v(1133) | Object km_idx is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : gpio.v(1144) | Object lm_idx is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : gpio.v(1155) | Object imb_idx is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : gpio.v(1165) | Object jmb_idx is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : gpio.v(1176) | Object kmb_idx is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : gpio.v(1187) | Object lmb_idx is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : gpio.v(1440) | Object i is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : gpio.v(1464) | Object j is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : gpio.v(1489) | Object k is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : gpio.v(1514) | Object l is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : gpio.v(1606) | Object iitb_idx is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : gpio.v(1618) | Object jitb_idx is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : gpio.v(1631) | Object kitb_idx is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : gpio.v(1644) | Object litb_idx is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : gpio.v(1773) | Object i_both is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : gpio.v(1796) | Object j_both is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : gpio.v(1820) | Object k_both is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : gpio.v(1844) | Object l_both is declared but not assigned. Either assign a value or remove the declaration.
@N:CG364 : gpio.v(80) | Synthesizing module gpio in library work.

	GPIO_WB_DAT_WIDTH=32'b00000000000000000000000000001000
	GPIO_WB_ADR_WIDTH=32'b00000000000000000000000000000100
	DATA_WIDTH=32'b00000000000000000000000000001000
	INPUT_WIDTH=32'b00000000000000000000000000000001
	OUTPUT_WIDTH=32'b00000000000000000000000000000001
	IRQ_MODE=32'b00000000000000000000000000000000
	LEVEL=32'b00000000000000000000000000000000
	EDGE=32'b00000000000000000000000000000001
	POSE_EDGE_IRQ=32'b00000000000000000000000000000001
	NEGE_EDGE_IRQ=32'b00000000000000000000000000000000
	EITHER_EDGE_IRQ=32'b00000000000000000000000000000000
	INPUT_PORTS_ONLY=32'b00000000000000000000000000000000
	OUTPUT_PORTS_ONLY=32'b00000000000000000000000000000001
	BOTH_INPUT_AND_OUTPUT=32'b00000000000000000000000000000000
	TRISTATE_PORTS=32'b00000000000000000000000000000000
	UDLY=32'b00000000000000000000000000000001
   Generated name = gpio_Z8_layer2

@W:CG133 : gpio.v(145) | Object PIO_DATAO is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : gpio.v(146) | Object PIO_DATAI is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : gpio.v(167) | Object IRQ_MASK is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : gpio.v(168) | Object IRQ_MASK_BOTH is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : gpio.v(169) | Object IRQ_TEMP is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : gpio.v(170) | Object IRQ_TEMP_BOTH is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : gpio.v(171) | Object EDGE_CAPTURE is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : gpio.v(172) | Object EDGE_CAPTURE_BOTH is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : gpio.v(173) | Object PIO_DATA_DLY is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : gpio.v(174) | Object PIO_DATA_DLY_BOTH is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : gpio.v(262) | Object jpd_idx is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : gpio.v(273) | Object kpd_idx is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : gpio.v(284) | Object lpd_idx is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : gpio.v(390) | Object iopd_idx is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : gpio.v(400) | Object jopd_idx is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : gpio.v(411) | Object kopd_idx is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : gpio.v(422) | Object lopd_idx is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : gpio.v(432) | Object mopd_idx is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : gpio.v(442) | Object nopd_idx is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : gpio.v(453) | Object oopd_idx is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : gpio.v(464) | Object popd_idx is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : gpio.v(672) | Object jti is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : gpio.v(700) | Object kti is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : gpio.v(728) | Object lti is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : gpio.v(1112) | Object im_idx is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : gpio.v(1122) | Object jm_idx is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : gpio.v(1133) | Object km_idx is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : gpio.v(1144) | Object lm_idx is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : gpio.v(1155) | Object imb_idx is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : gpio.v(1165) | Object jmb_idx is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : gpio.v(1176) | Object kmb_idx is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : gpio.v(1187) | Object lmb_idx is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : gpio.v(1440) | Object i is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : gpio.v(1464) | Object j is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : gpio.v(1489) | Object k is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : gpio.v(1514) | Object l is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : gpio.v(1606) | Object iitb_idx is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : gpio.v(1618) | Object jitb_idx is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : gpio.v(1631) | Object kitb_idx is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : gpio.v(1644) | Object litb_idx is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : gpio.v(1773) | Object i_both is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : gpio.v(1796) | Object j_both is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : gpio.v(1820) | Object k_both is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : gpio.v(1844) | Object l_both is declared but not assigned. Either assign a value or remove the declaration.
@N:CG364 : dos_gpio.v(332) | Synthesizing module dos_gpio in library work.

@W:CG781 : dos_gpio.v(557) | Input PIO_BOTH_IN on instance gpioent is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : dos_gpio.v(598) | Input PIO_IN on instance gpiosal is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : dos_gpio.v(598) | Input PIO_BOTH_IN on instance gpiosal is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG133 : dos_gpio.v(338) | Object i is declared but not assigned. Either assign a value or remove the declaration.
@W:CG360 : dos_gpio.v(354) | Removing wire SHAREDBUS_en, as there is no assignment to it.
@W:CL157 : gpio.v(124) | *Output PIO_BOTH_OUT has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@N:CL159 : gpio.v(104) | Input GPIO_CYC_I is unused.
@N:CL159 : gpio.v(107) | Input GPIO_LOCK_I is unused.
@N:CL159 : gpio.v(108) | Input GPIO_CTI_I is unused.
@N:CL159 : gpio.v(109) | Input GPIO_BTE_I is unused.
@N:CL159 : gpio.v(112) | Input GPIO_SEL_I is unused.
@N:CL159 : gpio.v(121) | Input PIO_IN is unused.
@N:CL159 : gpio.v(122) | Input PIO_BOTH_IN is unused.
@A:CL153 : tpio.v(109) | *Unassigned bits of IRQ_MASK are referenced and tied to 0 -- simulation mismatch possible.
@N:CL159 : tpio.v(98) | Input IRQ_MASK_WR_EN is unused.
@N:CL159 : tpio.v(99) | Input EDGE_CAP_WR_EN is unused.
@W:CL157 : gpio.v(123) | *Output PIO_OUT has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W:CL157 : gpio.v(124) | *Output PIO_BOTH_OUT has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@N:CL159 : gpio.v(104) | Input GPIO_CYC_I is unused.
@N:CL159 : gpio.v(107) | Input GPIO_LOCK_I is unused.
@N:CL159 : gpio.v(108) | Input GPIO_CTI_I is unused.
@N:CL159 : gpio.v(109) | Input GPIO_BTE_I is unused.
@N:CL159 : gpio.v(112) | Input GPIO_SEL_I is unused.
@N:CL159 : gpio.v(122) | Input PIO_BOTH_IN is unused.
@A:CL153 : lm8_top.v(86) | *Unassigned bits of I_CYC_O are referenced and tied to 0 -- simulation mismatch possible.
@A:CL153 : lm8_top.v(87) | *Unassigned bits of I_STB_O are referenced and tied to 0 -- simulation mismatch possible.
@A:CL153 : lm8_top.v(88) | *Unassigned bits of I_CTI_O[2:0] are referenced and tied to 0 -- simulation mismatch possible.
@A:CL153 : lm8_top.v(89) | *Unassigned bits of I_BTE_O[1:0] are referenced and tied to 0 -- simulation mismatch possible.
@A:CL153 : lm8_top.v(90) | *Unassigned bits of I_WE_O are referenced and tied to 0 -- simulation mismatch possible.
@A:CL153 : lm8_top.v(91) | *Unassigned bits of I_SEL_O are referenced and tied to 0 -- simulation mismatch possible.
@A:CL153 : lm8_top.v(92) | *Unassigned bits of I_DAT_O[7:0] are referenced and tied to 0 -- simulation mismatch possible.
@A:CL153 : lm8_top.v(93) | *Unassigned bits of I_ADR_O[31:0] are referenced and tied to 0 -- simulation mismatch possible.
@A:CL153 : lm8_top.v(94) | *Unassigned bits of I_LOCK_O are referenced and tied to 0 -- simulation mismatch possible.
@N:CL159 : lm8_top.v(82) | Input I_ACK_I is unused.
@N:CL159 : lm8_top.v(83) | Input I_ERR_I is unused.
@N:CL159 : lm8_top.v(84) | Input I_RTY_I is unused.
@N:CL159 : lm8_top.v(85) | Input I_DAT_I is unused.
@N:CL159 : lm8_top.v(97) | Input D_ERR_I is unused.
@N:CL159 : lm8_top.v(98) | Input D_RTY_I is unused.
@N:CL159 : lm8_flow_cntl.v(73) | Input prom_ready is unused.
@W:CL246 : lm8_alu.v(52) | Input port bits 13 to 2 of instr[17:0] are unused. Assign logic for all port bits or change the input port size.
@N:CL201 : dos_gpio.v(246) | Trying to extract state machine for register selected.
Extracted state machine for register selected
State machine has 3 reachable states with original encodings of:
   00
   01
   10

At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 77MB peak: 80MB)


Process completed successfully.
# Sat Sep 30 04:33:31 2017

###########################################################]
Synopsys Netlist Linker, version comp2016q2rc, Build 192R, built Jul  5 2016
@N: :  | Running in 64-bit mode 
File C:\TFG\exp4\esquema_con_gpio\synwork\layer0.srs changed - recompiling
File C:\TFG\exp4\esquema_con_gpio\synwork\layer1.srs changed - recompiling
File C:\TFG\exp4\esquema_con_gpio\synwork\layer2.srs changed - recompiling
@W:Z198 : div2.vhd(60) | Unbound component FD1P3DX of instance FF_0 
@W:Z198 : div2.vhd(67) | Unbound component FADD2B of instance cnt_cia 
@W:Z198 : div2.vhd(72) | Unbound component CU2 of instance cnt_0 
@W:Z198 : div2.vhd(76) | Unbound component VLO of instance scuba_vlo_inst 

=======================================================================================
For a summary of linker messages for components that did not bind, please see log file:
Linked File: esquema_con_gpio_esquema_con_gpio_comp.linkerlog
=======================================================================================


At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 69MB peak: 69MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Sat Sep 30 04:33:31 2017

###########################################################]
@END

At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 3MB peak: 4MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Sat Sep 30 04:33:31 2017

###########################################################]
Synopsys Netlist Linker, version comp2016q2rc, Build 192R, built Jul  5 2016
@N: :  | Running in 64-bit mode 
File C:\TFG\exp4\esquema_con_gpio\synwork\esquema_con_gpio_esquema_con_gpio_comp.srs changed - recompiling

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 69MB peak: 70MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Sat Sep 30 04:33:33 2017

###########################################################]
Pre-mapping Report

Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1498R, Built Jul  5 2016 10:30:31
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
Product Version L-2016.03L-1

Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

@A:MF827 :  | No constraint file specified. 
Linked File: esquema_con_gpio_esquema_con_gpio_scck.rpt
Printing clock  summary report in "C:\TFG\exp4\esquema_con_gpio\esquema_con_gpio_esquema_con_gpio_scck.rpt" file 
@N:MF248 :  | Running in 64-bit mode. 
@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 114MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 116MB)

ICG Latch Removal Summary:
Number of ICG latches removed:	0
Number of ICG latches not removed:	0
syn_allowed_resources : blockrams=26  set on top level netlist esquema_con_gpio

Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB)



Clock Summary
*****************

Start                            Requested     Requested     Clock                                       Clock                   Clock
Clock                            Frequency     Period        Type                                        Group                   Load 
--------------------------------------------------------------------------------------------------------------------------------------
System                           1.0 MHz       1000.000      system                                      system_clkgroup         0    
div2|tdataout0_derived_clock     1.0 MHz       1000.000      derived (from esquema_con_gpio|sal_osc)     Inferred_clkgroup_0     185  
esquema_con_gpio|sal_osc         1.0 MHz       1000.000      inferred                                    Inferred_clkgroup_0     1    
======================================================================================================================================

@W:MT529 : div2.vhd(60) | Found inferred clock esquema_con_gpio|sal_osc which controls 1 sequential elements including I25.FF_0. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 

Finished Pre Mapping Phase.

Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB)

Encoding state machine selected[2:0] (in view: work.arbiter2_8s_8s_8s_8s(verilog))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
None
None

Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB)

Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 57MB peak: 144MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Sat Sep 30 04:33:34 2017

###########################################################]
Map & Optimize Report

Synopsys Lattice Technology Mapper, Version maplat, Build 1498R, Built Jul  5 2016 10:30:31
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
Product Version L-2016.03L-1

Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

@N:MF248 :  | Running in 64-bit mode. 
@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 111MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 114MB)



Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)

@N:MO111 : gpio.v(124) | Tristate driver PIO_BOTH_OUT_1 (in view: work.gpio_Z7_layer2(verilog)) on net PIO_BOTH_OUT_1 (in view: work.gpio_Z7_layer2(verilog)) has its enable tied to GND.
@N:MO111 : gpio.v(123) | Tristate driver PIO_OUT_1 (in view: work.gpio_Z7_layer2(verilog)) on net PIO_OUT_1 (in view: work.gpio_Z7_layer2(verilog)) has its enable tied to GND.
@N:MO111 : gpio.v(123) | Tristate driver PIO_OUT_2 (in view: work.gpio_Z7_layer2(verilog)) on net PIO_OUT_2 (in view: work.gpio_Z7_layer2(verilog)) has its enable tied to GND.
@N:MO111 : gpio.v(123) | Tristate driver PIO_OUT_3 (in view: work.gpio_Z7_layer2(verilog)) on net PIO_OUT_3 (in view: work.gpio_Z7_layer2(verilog)) has its enable tied to GND.
@N:MO111 : gpio.v(123) | Tristate driver PIO_OUT_4 (in view: work.gpio_Z7_layer2(verilog)) on net PIO_OUT_4 (in view: work.gpio_Z7_layer2(verilog)) has its enable tied to GND.
@N:MO111 : gpio.v(123) | Tristate driver PIO_OUT_5 (in view: work.gpio_Z7_layer2(verilog)) on net PIO_OUT_5 (in view: work.gpio_Z7_layer2(verilog)) has its enable tied to GND.
@N:MO111 : gpio.v(123) | Tristate driver PIO_OUT_6 (in view: work.gpio_Z7_layer2(verilog)) on net PIO_OUT_6 (in view: work.gpio_Z7_layer2(verilog)) has its enable tied to GND.
@N:MO111 : gpio.v(123) | Tristate driver PIO_OUT_7 (in view: work.gpio_Z7_layer2(verilog)) on net PIO_OUT_7 (in view: work.gpio_Z7_layer2(verilog)) has its enable tied to GND.
@N:MO111 : gpio.v(123) | Tristate driver PIO_OUT_8 (in view: work.gpio_Z7_layer2(verilog)) on net PIO_OUT_8 (in view: work.gpio_Z7_layer2(verilog)) has its enable tied to GND.
@N:MO111 : gpio.v(124) | Tristate driver PIO_BOTH_OUT_1 (in view: work.gpio_Z8_layer2(verilog)) on net PIO_BOTH_OUT_1 (in view: work.gpio_Z8_layer2(verilog)) has its enable tied to GND.
@N:BN362 : tpio.v(126) | Removing sequential instance genblk9\.itio_inst\[3\]\.TP.PIO_DATA_I (in view: work.gpio_Z7_layer2(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : tpio.v(126) | Removing sequential instance genblk9\.itio_inst\[6\]\.TP.PIO_DATA_I (in view: work.gpio_Z7_layer2(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : tpio.v(126) | Removing sequential instance genblk9\.itio_inst\[4\]\.TP.PIO_DATA_I (in view: work.gpio_Z7_layer2(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : tpio.v(126) | Removing sequential instance genblk9\.itio_inst\[7\]\.TP.PIO_DATA_I (in view: work.gpio_Z7_layer2(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : tpio.v(126) | Removing sequential instance genblk9\.itio_inst\[2\]\.TP.PIO_DATA_I (in view: work.gpio_Z7_layer2(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : tpio.v(126) | Removing sequential instance genblk9\.itio_inst\[5\]\.TP.PIO_DATA_I (in view: work.gpio_Z7_layer2(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : tpio.v(126) | Removing sequential instance genblk9\.itio_inst\[1\]\.TP.PIO_DATA_I (in view: work.gpio_Z7_layer2(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : tpio.v(126) | Removing sequential instance genblk9\.itio_inst\[0\]\.TP.PIO_DATA_I (in view: work.gpio_Z7_layer2(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : tpio.v(126) | Removing sequential instance genblk9\.itio_inst\[3\]\.TP.PIO_DATA_I (in view: work.gpio_Z8_layer2(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : tpio.v(126) | Removing sequential instance genblk9\.itio_inst\[6\]\.TP.PIO_DATA_I (in view: work.gpio_Z8_layer2(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : tpio.v(126) | Removing sequential instance genblk9\.itio_inst\[0\]\.TP.PIO_DATA_I (in view: work.gpio_Z8_layer2(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : tpio.v(126) | Removing sequential instance genblk9\.itio_inst\[7\]\.TP.PIO_DATA_I (in view: work.gpio_Z8_layer2(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : tpio.v(126) | Removing sequential instance genblk9\.itio_inst\[2\]\.TP.PIO_DATA_I (in view: work.gpio_Z8_layer2(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : tpio.v(126) | Removing sequential instance genblk9\.itio_inst\[4\]\.TP.PIO_DATA_I (in view: work.gpio_Z8_layer2(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : tpio.v(126) | Removing sequential instance genblk9\.itio_inst\[1\]\.TP.PIO_DATA_I (in view: work.gpio_Z8_layer2(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : tpio.v(126) | Removing sequential instance genblk9\.itio_inst\[5\]\.TP.PIO_DATA_I (in view: work.gpio_Z8_layer2(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : tpio.v(120) | Removing sequential instance gpiosal.genblk9\.itio_inst\[3\]\.TP.PIO_DATA_O (in view: work.dos_gpio(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : tpio.v(114) | Removing sequential instance gpiosal.genblk9\.itio_inst\[3\]\.TP.PIO_TRI (in view: work.dos_gpio(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : tpio.v(120) | Removing sequential instance gpiosal.genblk9\.itio_inst\[6\]\.TP.PIO_DATA_O (in view: work.dos_gpio(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : tpio.v(114) | Removing sequential instance gpiosal.genblk9\.itio_inst\[6\]\.TP.PIO_TRI (in view: work.dos_gpio(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : tpio.v(120) | Removing sequential instance gpiosal.genblk9\.itio_inst\[0\]\.TP.PIO_DATA_O (in view: work.dos_gpio(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : tpio.v(114) | Removing sequential instance gpiosal.genblk9\.itio_inst\[0\]\.TP.PIO_TRI (in view: work.dos_gpio(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : tpio.v(120) | Removing sequential instance gpiosal.genblk9\.itio_inst\[7\]\.TP.PIO_DATA_O (in view: work.dos_gpio(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : tpio.v(114) | Removing sequential instance gpiosal.genblk9\.itio_inst\[7\]\.TP.PIO_TRI (in view: work.dos_gpio(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : tpio.v(120) | Removing sequential instance gpiosal.genblk9\.itio_inst\[2\]\.TP.PIO_DATA_O (in view: work.dos_gpio(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : tpio.v(114) | Removing sequential instance gpiosal.genblk9\.itio_inst\[2\]\.TP.PIO_TRI (in view: work.dos_gpio(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : tpio.v(120) | Removing sequential instance gpiosal.genblk9\.itio_inst\[4\]\.TP.PIO_DATA_O (in view: work.dos_gpio(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : tpio.v(114) | Removing sequential instance gpiosal.genblk9\.itio_inst\[4\]\.TP.PIO_TRI (in view: work.dos_gpio(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : tpio.v(120) | Removing sequential instance gpiosal.genblk9\.itio_inst\[1\]\.TP.PIO_DATA_O (in view: work.dos_gpio(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : tpio.v(114) | Removing sequential instance gpiosal.genblk9\.itio_inst\[1\]\.TP.PIO_TRI (in view: work.dos_gpio(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : tpio.v(120) | Removing sequential instance gpiosal.genblk9\.itio_inst\[5\]\.TP.PIO_DATA_O (in view: work.dos_gpio(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : tpio.v(114) | Removing sequential instance gpiosal.genblk9\.itio_inst\[5\]\.TP.PIO_TRI (in view: work.dos_gpio(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : tpio.v(120) | Removing sequential instance gpioent.genblk9\.itio_inst\[3\]\.TP.PIO_DATA_O (in view: work.dos_gpio(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : tpio.v(114) | Removing sequential instance gpioent.genblk9\.itio_inst\[3\]\.TP.PIO_TRI (in view: work.dos_gpio(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : tpio.v(120) | Removing sequential instance gpioent.genblk9\.itio_inst\[6\]\.TP.PIO_DATA_O (in view: work.dos_gpio(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : tpio.v(114) | Removing sequential instance gpioent.genblk9\.itio_inst\[6\]\.TP.PIO_TRI (in view: work.dos_gpio(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : tpio.v(120) | Removing sequential instance gpioent.genblk9\.itio_inst\[4\]\.TP.PIO_DATA_O (in view: work.dos_gpio(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : tpio.v(114) | Removing sequential instance gpioent.genblk9\.itio_inst\[4\]\.TP.PIO_TRI (in view: work.dos_gpio(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : tpio.v(120) | Removing sequential instance gpioent.genblk9\.itio_inst\[7\]\.TP.PIO_DATA_O (in view: work.dos_gpio(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : tpio.v(114) | Removing sequential instance gpioent.genblk9\.itio_inst\[7\]\.TP.PIO_TRI (in view: work.dos_gpio(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : tpio.v(120) | Removing sequential instance gpioent.genblk9\.itio_inst\[2\]\.TP.PIO_DATA_O (in view: work.dos_gpio(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : tpio.v(114) | Removing sequential instance gpioent.genblk9\.itio_inst\[2\]\.TP.PIO_TRI (in view: work.dos_gpio(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : tpio.v(120) | Removing sequential instance gpioent.genblk9\.itio_inst\[5\]\.TP.PIO_DATA_O (in view: work.dos_gpio(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : tpio.v(114) | Removing sequential instance gpioent.genblk9\.itio_inst\[5\]\.TP.PIO_TRI (in view: work.dos_gpio(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : tpio.v(120) | Removing sequential instance gpioent.genblk9\.itio_inst\[1\]\.TP.PIO_DATA_O (in view: work.dos_gpio(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : tpio.v(114) | Removing sequential instance gpioent.genblk9\.itio_inst\[1\]\.TP.PIO_TRI (in view: work.dos_gpio(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : tpio.v(120) | Removing sequential instance gpioent.genblk9\.itio_inst\[0\]\.TP.PIO_DATA_O (in view: work.dos_gpio(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : tpio.v(114) | Removing sequential instance gpioent.genblk9\.itio_inst\[0\]\.TP.PIO_TRI (in view: work.dos_gpio(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.

Available hyper_sources - for debug and ip models
	None Found


Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 142MB)

Encoding state machine selected[2:0] (in view: work.arbiter2_8s_8s_8s_8s(verilog))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
@W:MO160 : dos_gpio.v(246) | Register bit selected[0] (in view view:work.arbiter2_8s_8s_8s_8s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.

Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 142MB)

@W:BN132 : lm8_flow_cntl.v(507) | Removing instance I1.lm8_inst.LM8.u1_isp8_core.u1_lm8_flow_cntl.dout_alu_reg[0] because it is equivalent to instance I1.lm8_inst.LM8.u1_isp8_core.din_rd1[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : lm8_flow_cntl.v(507) | Removing instance I1.lm8_inst.LM8.u1_isp8_core.u1_lm8_flow_cntl.dout_alu_reg[1] because it is equivalent to instance I1.lm8_inst.LM8.u1_isp8_core.din_rd1[1]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : lm8_flow_cntl.v(507) | Removing instance I1.lm8_inst.LM8.u1_isp8_core.u1_lm8_flow_cntl.dout_alu_reg[2] because it is equivalent to instance I1.lm8_inst.LM8.u1_isp8_core.din_rd1[2]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : lm8_flow_cntl.v(507) | Removing instance I1.lm8_inst.LM8.u1_isp8_core.u1_lm8_flow_cntl.dout_alu_reg[3] because it is equivalent to instance I1.lm8_inst.LM8.u1_isp8_core.din_rd1[3]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : lm8_flow_cntl.v(507) | Removing instance I1.lm8_inst.LM8.u1_isp8_core.u1_lm8_flow_cntl.dout_alu_reg[4] because it is equivalent to instance I1.lm8_inst.LM8.u1_isp8_core.din_rd1[4]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : lm8_flow_cntl.v(507) | Removing instance I1.lm8_inst.LM8.u1_isp8_core.u1_lm8_flow_cntl.dout_alu_reg[5] because it is equivalent to instance I1.lm8_inst.LM8.u1_isp8_core.din_rd1[5]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : lm8_flow_cntl.v(507) | Removing instance I1.lm8_inst.LM8.u1_isp8_core.u1_lm8_flow_cntl.dout_alu_reg[6] because it is equivalent to instance I1.lm8_inst.LM8.u1_isp8_core.din_rd1[6]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : lm8_flow_cntl.v(507) | Removing instance I1.lm8_inst.LM8.u1_isp8_core.u1_lm8_flow_cntl.dout_alu_reg[7] because it is equivalent to instance I1.lm8_inst.LM8.u1_isp8_core.din_rd1[7]. To keep the instance, apply constraint syn_preserve=1 on the instance.

Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 146MB peak: 147MB)


Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 147MB)


Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 148MB)

@N:FA113 : lm8_flow_cntl.v(410) | Pipelining module un1_stack_ptr[3:0]. For more information, search for "pipelining" in Online Help.
@N:MF169 : lm8_flow_cntl.v(507) | Pushed in register stack_ptr[3:0].
@N:BN362 : lm8_interrupt.v(122) | Removing sequential instance I1.lm8_inst.LM8.u1_isp8_core.u1_lm8_interrupt.ip[2] (in view: work.esquema_con_gpio(verilog)) because it does not drive other instances.
@N:BN362 : lm8_interrupt.v(122) | Removing sequential instance I1.lm8_inst.LM8.u1_isp8_core.u1_lm8_interrupt.ip[1] (in view: work.esquema_con_gpio(verilog)) because it does not drive other instances.
@N:BN362 : lm8_interrupt.v(122) | Removing sequential instance I1.lm8_inst.LM8.u1_isp8_core.u1_lm8_interrupt.ip[0] (in view: work.esquema_con_gpio(verilog)) because it does not drive other instances.
@N:BN362 : lm8_interrupt.v(122) | Removing sequential instance I1.lm8_inst.LM8.u1_isp8_core.u1_lm8_interrupt.ip[7] (in view: work.esquema_con_gpio(verilog)) because it does not drive other instances.
@N:BN362 : lm8_interrupt.v(122) | Removing sequential instance I1.lm8_inst.LM8.u1_isp8_core.u1_lm8_interrupt.ip[6] (in view: work.esquema_con_gpio(verilog)) because it does not drive other instances.
@N:BN362 : lm8_interrupt.v(122) | Removing sequential instance I1.lm8_inst.LM8.u1_isp8_core.u1_lm8_interrupt.ip[5] (in view: work.esquema_con_gpio(verilog)) because it does not drive other instances.
@N:BN362 : lm8_interrupt.v(122) | Removing sequential instance I1.lm8_inst.LM8.u1_isp8_core.u1_lm8_interrupt.ip[4] (in view: work.esquema_con_gpio(verilog)) because it does not drive other instances.
@N:BN362 : lm8_interrupt.v(122) | Removing sequential instance I1.lm8_inst.LM8.u1_isp8_core.u1_lm8_interrupt.ip[3] (in view: work.esquema_con_gpio(verilog)) because it does not drive other instances.
@N:BN362 : lm8_flow_cntl.v(507) | Removing sequential instance I1.lm8_inst.LM8.u1_isp8_core.u1_lm8_flow_cntl.intr_ack (in view: work.esquema_con_gpio(verilog)) because it does not drive other instances.

Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 148MB)


Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 148MB)


Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 148MB)


Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 148MB)


Finished technology mapping (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 167MB peak: 169MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:02s		   981.82ns		 263 /       119

Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 167MB peak: 169MB)

@N:FX164 :  | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.   

Finished restoring hierarchy (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 167MB peak: 169MB)



@S |Clock Optimization Summary


#### START OF CLOCK OPTIMIZATION REPORT #####[

2 non-gated/non-generated clock tree(s) driving 120 clock pin(s) of sequential element(s)
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
0 instances converted, 0 sequential instances remain driven by gated/generated clocks

=============================================== Non-Gated/Non-Generated Clocks ================================================
Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance                                        
-------------------------------------------------------------------------------------------------------------------------------
ClockId0001        sal_osc             port                   1          I25.FF_0                                               
ClockId0002        I25.FF_0            FD1P3DX                119        I1.lm8_inst.LM8.u1_isp8_core.u1_lm8_flow_cntl.rst_n_reg
===============================================================================================================================


##### END OF CLOCK OPTIMIZATION REPORT ######]


Start Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 133MB peak: 169MB)

Writing Analyst data base C:\TFG\exp4\esquema_con_gpio\synwork\esquema_con_gpio_esquema_con_gpio_m.srm

Finished Writing Netlist Databases (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 165MB peak: 169MB)

Writing EDIF Netlist and constraint files
@N:FX1056 :  | Writing EDF file: C:\TFG\exp4\esquema_con_gpio\esquema_con_gpio_esquema_con_gpio.edi 
L-2016.03L-1
@N:BW106 :  | Synplicity Constraint File capacitance units using default value of 1pF  

Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 169MB peak: 171MB)


Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 169MB peak: 171MB)

@W:MT246 : lm8_top.v(607) | Blackbox pmi_ram_dq_Z6_layer2 is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@W:MT246 : lm8_top.v(377) | Blackbox pmi_ram_dq_Z5_layer2 is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@W:MT246 : lm8_core.v(534) | Blackbox pmi_distributed_dpram_32s_5s_8s_noreg_none_binary_EC_pmi_distributed_dpram_3_layer2 is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@W:MT246 : lm8_flow_cntl.v(456) | Blackbox pmi_distributed_spram_16s_4s_13s_noreg_none_binary_EC_pmi_distributed_spram_1_layer2 is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@W:MT246 : lm8_alu.v(102) | Blackbox pmi_addsub_8s_8s_off_EC_pmi_addsub is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@W:MT420 :  | Found inferred clock esquema_con_gpio|sal_osc with period 1000.00ns. Please declare a user-defined clock on object "p:sal_osc" 
@N:MT615 :  | Found clock div2|tdataout0_derived_clock with period 1000.00ns  


##### START OF TIMING REPORT #####[
# Timing Report written on Sat Sep 30 04:33:38 2017
#


Top view:               esquema_con_gpio
Requested Frequency:    1.0 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    
@N:MT320 :  | Timing report estimates place and route data. Please look at the place and route timing report for final timing. 

@N:MT322 :  | Clock constraints cover only FF-to-FF paths associated with the clock. 



Performance Summary
*******************


Worst slack in design: 985.478

                                 Requested     Estimated     Requested     Estimated                  Clock                                       Clock              
Starting Clock                   Frequency     Frequency     Period        Period        Slack        Type                                        Group              
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
div2|tdataout0_derived_clock     1.0 MHz       136.7 MHz     1000.000      7.314         1985.372     derived (from esquema_con_gpio|sal_osc)     Inferred_clkgroup_0
esquema_con_gpio|sal_osc         1.0 MHz       NA            1000.000      NA            DCM/PLL      inferred                                    Inferred_clkgroup_0
System                           1.0 MHz       76.0 MHz      1000.000      13.154        986.846      system                                      system_clkgroup    
=====================================================================================================================================================================
@N:MT582 :  | Estimated period and frequency not reported for given clock unless the clock has at least one timing path which is not a false or a max delay path and that does not have excessive slack 





Clock Relationships
*******************

Clocks                                                      |    rise  to  rise      |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
-----------------------------------------------------------------------------------------------------------------------------------------------------
Starting                      Ending                        |  constraint  slack     |  constraint  slack  |  constraint  slack  |  constraint  slack
-----------------------------------------------------------------------------------------------------------------------------------------------------
System                        System                        |  1000.000    986.846   |  No paths    -      |  No paths    -      |  No paths    -    
System                        div2|tdataout0_derived_clock  |  1000.000    986.740   |  No paths    -      |  No paths    -      |  No paths    -    
div2|tdataout0_derived_clock  System                        |  1000.000    985.478   |  No paths    -      |  No paths    -      |  No paths    -    
div2|tdataout0_derived_clock  div2|tdataout0_derived_clock  |  1000.000    1985.372  |  No paths    -      |  No paths    -      |  No paths    -    
=====================================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

No IO constraint found



====================================
Detailed Report for Clock: div2|tdataout0_derived_clock
====================================



Starting Points with Worst Slack
********************************

                                                           Starting                                                              Arrival            
Instance                                                   Reference                        Type        Pin     Net              Time        Slack  
                                                           Clock                                                                                    
----------------------------------------------------------------------------------------------------------------------------------------------------
I1.lm8_inst.LM8.genblk1\.first_fetch                       div2|tdataout0_derived_clock     FD1S3DX     Q       first_fetch      1.368       985.478
I1.lm8_inst.LM8.u1_isp8_core.genblk2\.page_ptr1[3]         div2|tdataout0_derived_clock     FD1P3DX     Q       page_ptr1[3]     1.044       989.604
I1.lm8_inst.LM8.u1_isp8_core.genblk2\.page_ptr1[6]         div2|tdataout0_derived_clock     FD1P3DX     Q       page_ptr1[6]     1.044       989.604
I1.lm8_inst.LM8.u1_isp8_core.genblk2\.page_ptr1[7]         div2|tdataout0_derived_clock     FD1P3DX     Q       page_ptr1[7]     1.044       989.604
I1.lm8_inst.LM8.u1_isp8_core.genblk2\.page_ptr1[4]         div2|tdataout0_derived_clock     FD1P3DX     Q       page_ptr1[4]     1.044       990.621
I1.lm8_inst.LM8.u1_isp8_core.genblk2\.page_ptr1[5]         div2|tdataout0_derived_clock     FD1P3DX     Q       page_ptr1[5]     1.044       990.621
I1.lm8_inst.LM8.u1_isp8_core.u1_lm8_cntl_u1.ext_io_wr      div2|tdataout0_derived_clock     FD1S3DX     Q       ext_io_wr        1.108       990.685
I1.lm8_inst.LM8.u1_isp8_core.u1_lm8_cntl_u1.ext_mem_wr     div2|tdataout0_derived_clock     FD1S3DX     Q       ext_mem_wr       1.180       990.749
I1.lm8_inst.LM8.u1_isp8_core.u1_lm8_cntl_u1.ext_io_rd      div2|tdataout0_derived_clock     FD1S3DX     Q       ext_io_rd        0.972       990.821
I1.lm8_inst.LM8.u1_isp8_core.u1_lm8_cntl_u1.ext_mem_rd     div2|tdataout0_derived_clock     FD1S3DX     Q       ext_mem_rd       1.044       990.885
====================================================================================================================================================


Ending Points with Worst Slack
******************************

                                                                Starting                                                                                                                                           Required            
Instance                                                        Reference                        Type                                                                                    Pin         Net           Time         Slack  
                                                                Clock                                                                                                                                                                  
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
I1.lm8_inst.LM8.u1_isp8_core.genblk6\.genblk1\.u1_lm8_rfmem     div2|tdataout0_derived_clock     pmi_distributed_dpram_32s_5s_8s_noreg_none_binary_EC_pmi_distributed_dpram_3_layer2     Data[0]     din_rd[0]     1000.000     985.478
I1.lm8_inst.LM8.u1_isp8_core.genblk6\.genblk1\.u1_lm8_rfmem     div2|tdataout0_derived_clock     pmi_distributed_dpram_32s_5s_8s_noreg_none_binary_EC_pmi_distributed_dpram_3_layer2     Data[1]     din_rd[1]     1000.000     985.478
I1.lm8_inst.LM8.u1_isp8_core.genblk6\.genblk1\.u1_lm8_rfmem     div2|tdataout0_derived_clock     pmi_distributed_dpram_32s_5s_8s_noreg_none_binary_EC_pmi_distributed_dpram_3_layer2     Data[2]     din_rd[2]     1000.000     985.478
I1.lm8_inst.LM8.u1_isp8_core.genblk6\.genblk1\.u1_lm8_rfmem     div2|tdataout0_derived_clock     pmi_distributed_dpram_32s_5s_8s_noreg_none_binary_EC_pmi_distributed_dpram_3_layer2     Data[3]     din_rd[3]     1000.000     985.478
I1.lm8_inst.LM8.u1_isp8_core.genblk6\.genblk1\.u1_lm8_rfmem     div2|tdataout0_derived_clock     pmi_distributed_dpram_32s_5s_8s_noreg_none_binary_EC_pmi_distributed_dpram_3_layer2     Data[4]     din_rd[4]     1000.000     985.478
I1.lm8_inst.LM8.u1_isp8_core.genblk6\.genblk1\.u1_lm8_rfmem     div2|tdataout0_derived_clock     pmi_distributed_dpram_32s_5s_8s_noreg_none_binary_EC_pmi_distributed_dpram_3_layer2     Data[5]     din_rd[5]     1000.000     985.478
I1.lm8_inst.LM8.u1_isp8_core.genblk6\.genblk1\.u1_lm8_rfmem     div2|tdataout0_derived_clock     pmi_distributed_dpram_32s_5s_8s_noreg_none_binary_EC_pmi_distributed_dpram_3_layer2     Data[6]     din_rd[6]     1000.000     985.478
I1.lm8_inst.LM8.u1_isp8_core.genblk6\.genblk1\.u1_lm8_rfmem     div2|tdataout0_derived_clock     pmi_distributed_dpram_32s_5s_8s_noreg_none_binary_EC_pmi_distributed_dpram_3_layer2     Data[7]     din_rd[7]     1000.000     985.478
I1.lm8_inst.LM8.u1_isp8_core.genblk6\.genblk1\.u2_lm8_rfmem     div2|tdataout0_derived_clock     pmi_distributed_dpram_32s_5s_8s_noreg_none_binary_EC_pmi_distributed_dpram_3_layer2     Data[0]     din_rd[0]     1000.000     985.478
I1.lm8_inst.LM8.u1_isp8_core.genblk6\.genblk1\.u2_lm8_rfmem     div2|tdataout0_derived_clock     pmi_distributed_dpram_32s_5s_8s_noreg_none_binary_EC_pmi_distributed_dpram_3_layer2     Data[1]     din_rd[1]     1000.000     985.478
=======================================================================================================================================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      1000.000
    - Setup time:                            0.000
    + Clock delay at ending point:           0.000 (ideal)
    + Estimated clock delay at ending point: 0.000
    = Required time:                         1000.000

    - Propagation time:                      14.522
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     985.478

    Number of logic level(s):                13
    Starting point:                          I1.lm8_inst.LM8.genblk1\.first_fetch / Q
    Ending point:                            I1.lm8_inst.LM8.u1_isp8_core.genblk6\.genblk1\.u1_lm8_rfmem / Data[0]
    The start point is clocked by            div2|tdataout0_derived_clock [rising] on pin CK
    The end   point is clocked by            System [rising]

Instance / Net                                                                                                                                          Pin         Pin               Arrival     No. of    
Name                                                            Type                                                                                    Name        Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
I1.lm8_inst.LM8.genblk1\.first_fetch                            FD1S3DX                                                                                 Q           Out     1.368     1.368       -         
first_fetch                                                     Net                                                                                     -           -       -         -           59        
I1.lm8_inst.LM8.u1_isp8_core.u1_lm8_idec.instr_l2_3             ORCALUT4                                                                                C           In      0.000     1.368       -         
I1.lm8_inst.LM8.u1_isp8_core.u1_lm8_idec.instr_l2_3             ORCALUT4                                                                                Z           Out     1.233     2.601       -         
instr_l2_3                                                      Net                                                                                     -           -       -         -           6         
I1.lm8_inst.LM8.u1_isp8_core.u1_lm8_idec.iels                   ORCALUT4                                                                                D           In      0.000     2.601       -         
I1.lm8_inst.LM8.u1_isp8_core.u1_lm8_idec.iels                   ORCALUT4                                                                                Z           Out     1.265     3.865       -         
iels                                                            Net                                                                                     -           -       -         -           8         
I1.lm8_inst.LM8.u1_isp8_core.genblk1\.ext_addr8                 ORCALUT4                                                                                B           In      0.000     3.865       -         
I1.lm8_inst.LM8.u1_isp8_core.genblk1\.ext_addr8                 ORCALUT4                                                                                Z           Out     1.305     5.170       -         
ext_addr8                                                       Net                                                                                     -           -       -         -           15        
I1.lm8_inst.LM8.genblk3\.genblk1\.un12_external_sp_2            ORCALUT4                                                                                A           In      0.000     5.170       -         
I1.lm8_inst.LM8.genblk3\.genblk1\.un12_external_sp_2            ORCALUT4                                                                                Z           Out     1.017     6.187       -         
un12_external_sp_2                                              Net                                                                                     -           -       -         -           1         
I1.lm8_inst.LM8.genblk3\.genblk1\.un12_external_sp              ORCALUT4                                                                                A           In      0.000     6.187       -         
I1.lm8_inst.LM8.genblk3\.genblk1\.un12_external_sp              ORCALUT4                                                                                Z           Out     1.281     7.468       -         
un12_external_sp                                                Net                                                                                     -           -       -         -           11        
I1.lm8_inst.LM8.ext_cyc                                         ORCALUT4                                                                                D           In      0.000     7.468       -         
I1.lm8_inst.LM8.ext_cyc                                         ORCALUT4                                                                                Z           Out     1.153     8.621       -         
ext_cyc                                                         Net                                                                                     -           -       -         -           3         
I1.lm8_inst.LM8.genblk2\.D_CYC_O4                               ORCALUT4                                                                                A           In      0.000     8.621       -         
I1.lm8_inst.LM8.genblk2\.D_CYC_O4                               ORCALUT4                                                                                Z           Out     0.449     9.069       -         
LM8D_STB_O                                                      Net                                                                                     -           -       -         -           4         
I1.lm8_inst.gpioentGPIO_en_11                                   ORCALUT4                                                                                A           In      0.000     9.069       -         
I1.lm8_inst.gpioentGPIO_en_11                                   ORCALUT4                                                                                Z           Out     1.193     10.262      -         
gpiosalGPIO_en_11                                               Net                                                                                     -           -       -         -           4         
I1.lm8_inst.gpioentGPIO_en                                      ORCALUT4                                                                                D           In      0.000     10.262      -         
I1.lm8_inst.gpioentGPIO_en                                      ORCALUT4                                                                                Z           Out     1.193     11.455      -         
gpioentGPIO_en                                                  Net                                                                                     -           -       -         -           4         
I1.lm8_inst.gpioent.read_byte_0                                 ORCALUT4                                                                                D           In      0.000     11.455      -         
I1.lm8_inst.gpioent.read_byte_0                                 ORCALUT4                                                                                Z           Out     0.449     11.904      -         
read_byte_0                                                     Net                                                                                     -           -       -         -           16        
I1.lm8_inst.LM8.ext_io_din[0]                                   ORCALUT4                                                                                C           In      0.000     11.904      -         
I1.lm8_inst.LM8.ext_io_din[0]                                   ORCALUT4                                                                                Z           Out     0.449     12.353      -         
ext_io_din[0]                                                   Net                                                                                     -           -       -         -           2         
I1.lm8_inst.LM8.u1_isp8_core.din_rd_iv_RNO[0]                   ORCALUT4                                                                                A           In      0.000     12.353      -         
I1.lm8_inst.LM8.u1_isp8_core.din_rd_iv_RNO[0]                   ORCALUT4                                                                                Z           Out     1.017     13.369      -         
ext_mem_din_m[0]                                                Net                                                                                     -           -       -         -           1         
I1.lm8_inst.LM8.u1_isp8_core.din_rd_iv[0]                       ORCALUT4                                                                                C           In      0.000     13.369      -         
I1.lm8_inst.LM8.u1_isp8_core.din_rd_iv[0]                       ORCALUT4                                                                                Z           Out     1.153     14.522      -         
din_rd[0]                                                       Net                                                                                     -           -       -         -           3         
I1.lm8_inst.LM8.u1_isp8_core.genblk6\.genblk1\.u1_lm8_rfmem     pmi_distributed_dpram_32s_5s_8s_noreg_none_binary_EC_pmi_distributed_dpram_3_layer2     Data[0]     In      0.000     14.522      -         
============================================================================================================================================================================================================




====================================
Detailed Report for Clock: System
====================================



Starting Points with Worst Slack
********************************

                                          Starting                                                               Arrival            
Instance                                  Reference     Type                     Pin       Net                   Time        Slack  
                                          Clock                                                                                     
------------------------------------------------------------------------------------------------------------------------------------
I1.lm8_inst.LM8.genblk1\.u1_isp8_prom     System        pmi_ram_dq_Z5_layer2     Q[14]     instr_mem_out[14]     0.000       986.740
I1.lm8_inst.LM8.genblk1\.u1_isp8_prom     System        pmi_ram_dq_Z5_layer2     Q[15]     instr_mem_out[15]     0.000       986.740
I1.lm8_inst.LM8.genblk1\.u1_isp8_prom     System        pmi_ram_dq_Z5_layer2     Q[17]     instr_mem_out[17]     0.000       987.524
I1.lm8_inst.LM8.genblk1\.u1_isp8_prom     System        pmi_ram_dq_Z5_layer2     Q[13]     instr_mem_out[13]     0.000       987.973
I1.lm8_inst.LM8.genblk1\.u1_isp8_prom     System        pmi_ram_dq_Z5_layer2     Q[16]     instr_mem_out[16]     0.000       987.973
I1.lm8_inst.LM8.genblk1\.u1_isp8_prom     System        pmi_ram_dq_Z5_layer2     Q[0]      instr_mem_out[0]      0.000       988.789
I1.lm8_inst.LM8.genblk1\.u1_isp8_prom     System        pmi_ram_dq_Z5_layer2     Q[1]      instr_mem_out[1]      0.000       988.789
I1.lm8_inst.LM8.genblk1\.u1_isp8_prom     System        pmi_ram_dq_Z5_layer2     Q[2]      instr_mem_out[2]      0.000       993.274
I1.lm8_inst.LM8.genblk1\.u1_isp8_prom     System        pmi_ram_dq_Z5_layer2     Q[12]     instr_mem_out[12]     0.000       995.269
I1.lm8_inst.LM8.genblk1\.u1_isp8_prom     System        pmi_ram_dq_Z5_layer2     Q[3]      instr_mem_out[3]      0.000       995.810
====================================================================================================================================


Ending Points with Worst Slack
******************************

                                                                Starting                                                                                                                        Required            
Instance                                                        Reference     Type                                                                                    Pin         Net           Time         Slack  
                                                                Clock                                                                                                                                               
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
I1.lm8_inst.LM8.u1_isp8_core.genblk2\.page_ptr1[0]              System        FD1P3DX                                                                                 D           din_rd[0]     999.894      986.740
I1.lm8_inst.LM8.u1_isp8_core.genblk2\.page_ptr1[1]              System        FD1P3DX                                                                                 D           din_rd[1]     999.894      986.740
I1.lm8_inst.LM8.u1_isp8_core.genblk2\.page_ptr1[2]              System        FD1P3DX                                                                                 D           din_rd[2]     999.894      986.740
I1.lm8_inst.LM8.u1_isp8_core.genblk2\.page_ptr1[3]              System        FD1P3DX                                                                                 D           din_rd[3]     999.894      986.740
I1.lm8_inst.LM8.u1_isp8_core.genblk2\.page_ptr1[4]              System        FD1P3DX                                                                                 D           din_rd[4]     999.894      986.740
I1.lm8_inst.LM8.u1_isp8_core.genblk2\.page_ptr1[5]              System        FD1P3DX                                                                                 D           din_rd[5]     999.894      986.740
I1.lm8_inst.LM8.u1_isp8_core.genblk2\.page_ptr1[6]              System        FD1P3DX                                                                                 D           din_rd[6]     999.894      986.740
I1.lm8_inst.LM8.u1_isp8_core.genblk2\.page_ptr1[7]              System        FD1P3DX                                                                                 D           din_rd[7]     999.894      986.740
I1.lm8_inst.LM8.u1_isp8_core.genblk6\.genblk1\.u1_lm8_rfmem     System        pmi_distributed_dpram_32s_5s_8s_noreg_none_binary_EC_pmi_distributed_dpram_3_layer2     Data[0]     din_rd[0]     1000.000     986.846
I1.lm8_inst.LM8.u1_isp8_core.genblk6\.genblk1\.u1_lm8_rfmem     System        pmi_distributed_dpram_32s_5s_8s_noreg_none_binary_EC_pmi_distributed_dpram_3_layer2     Data[1]     din_rd[1]     1000.000     986.846
====================================================================================================================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      1000.000
    - Setup time:                            0.106
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         999.894

    - Propagation time:                      13.154
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 986.740

    Number of logic level(s):                13
    Starting point:                          I1.lm8_inst.LM8.genblk1\.u1_isp8_prom / Q[14]
    Ending point:                            I1.lm8_inst.LM8.u1_isp8_core.genblk2\.page_ptr1[0] / D
    The start point is clocked by            System [rising]
    The end   point is clocked by            div2|tdataout0_derived_clock [rising] on pin CK

Instance / Net                                                                    Pin       Pin               Arrival     No. of    
Name                                                     Type                     Name      Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------------------------------------------------------
I1.lm8_inst.LM8.genblk1\.u1_isp8_prom                    pmi_ram_dq_Z5_layer2     Q[14]     Out     0.000     0.000       -         
instr_mem_out[14]                                        Net                      -         -       -         -           4         
I1.lm8_inst.LM8.u1_isp8_core.u1_lm8_idec.instr_l2_3      ORCALUT4                 A         In      0.000     0.000       -         
I1.lm8_inst.LM8.u1_isp8_core.u1_lm8_idec.instr_l2_3      ORCALUT4                 Z         Out     1.233     1.233       -         
instr_l2_3                                               Net                      -         -       -         -           6         
I1.lm8_inst.LM8.u1_isp8_core.u1_lm8_idec.iels            ORCALUT4                 D         In      0.000     1.233       -         
I1.lm8_inst.LM8.u1_isp8_core.u1_lm8_idec.iels            ORCALUT4                 Z         Out     1.265     2.498       -         
iels                                                     Net                      -         -       -         -           8         
I1.lm8_inst.LM8.u1_isp8_core.genblk1\.ext_addr8          ORCALUT4                 B         In      0.000     2.498       -         
I1.lm8_inst.LM8.u1_isp8_core.genblk1\.ext_addr8          ORCALUT4                 Z         Out     1.305     3.802       -         
ext_addr8                                                Net                      -         -       -         -           15        
I1.lm8_inst.LM8.genblk3\.genblk1\.un12_external_sp_2     ORCALUT4                 A         In      0.000     3.802       -         
I1.lm8_inst.LM8.genblk3\.genblk1\.un12_external_sp_2     ORCALUT4                 Z         Out     1.017     4.819       -         
un12_external_sp_2                                       Net                      -         -       -         -           1         
I1.lm8_inst.LM8.genblk3\.genblk1\.un12_external_sp       ORCALUT4                 A         In      0.000     4.819       -         
I1.lm8_inst.LM8.genblk3\.genblk1\.un12_external_sp       ORCALUT4                 Z         Out     1.281     6.100       -         
un12_external_sp                                         Net                      -         -       -         -           11        
I1.lm8_inst.LM8.ext_cyc                                  ORCALUT4                 D         In      0.000     6.100       -         
I1.lm8_inst.LM8.ext_cyc                                  ORCALUT4                 Z         Out     1.153     7.253       -         
ext_cyc                                                  Net                      -         -       -         -           3         
I1.lm8_inst.LM8.genblk2\.D_CYC_O4                        ORCALUT4                 A         In      0.000     7.253       -         
I1.lm8_inst.LM8.genblk2\.D_CYC_O4                        ORCALUT4                 Z         Out     0.449     7.702       -         
LM8D_STB_O                                               Net                      -         -       -         -           4         
I1.lm8_inst.gpioentGPIO_en_11                            ORCALUT4                 A         In      0.000     7.702       -         
I1.lm8_inst.gpioentGPIO_en_11                            ORCALUT4                 Z         Out     1.193     8.894       -         
gpiosalGPIO_en_11                                        Net                      -         -       -         -           4         
I1.lm8_inst.gpioentGPIO_en                               ORCALUT4                 D         In      0.000     8.894       -         
I1.lm8_inst.gpioentGPIO_en                               ORCALUT4                 Z         Out     1.193     10.087      -         
gpioentGPIO_en                                           Net                      -         -       -         -           4         
I1.lm8_inst.gpioent.read_byte_0                          ORCALUT4                 D         In      0.000     10.087      -         
I1.lm8_inst.gpioent.read_byte_0                          ORCALUT4                 Z         Out     0.449     10.536      -         
read_byte_0                                              Net                      -         -       -         -           16        
I1.lm8_inst.LM8.ext_io_din[0]                            ORCALUT4                 C         In      0.000     10.536      -         
I1.lm8_inst.LM8.ext_io_din[0]                            ORCALUT4                 Z         Out     0.449     10.985      -         
ext_io_din[0]                                            Net                      -         -       -         -           2         
I1.lm8_inst.LM8.u1_isp8_core.din_rd_iv_RNO[0]            ORCALUT4                 A         In      0.000     10.985      -         
I1.lm8_inst.LM8.u1_isp8_core.din_rd_iv_RNO[0]            ORCALUT4                 Z         Out     1.017     12.002      -         
ext_mem_din_m[0]                                         Net                      -         -       -         -           1         
I1.lm8_inst.LM8.u1_isp8_core.din_rd_iv[0]                ORCALUT4                 C         In      0.000     12.002      -         
I1.lm8_inst.LM8.u1_isp8_core.din_rd_iv[0]                ORCALUT4                 Z         Out     1.153     13.154      -         
din_rd[0]                                                Net                      -         -       -         -           3         
I1.lm8_inst.LM8.u1_isp8_core.genblk2\.page_ptr1[0]       FD1P3DX                  D         In      0.000     13.154      -         
====================================================================================================================================



##### END OF TIMING REPORT #####]

Constraints that could not be applied
None

Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 169MB peak: 171MB)


Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 169MB peak: 171MB)

---------------------------------------
Resource Usage Report
Part: lcmxo2_7000he-4

Register bits: 120 of 6864 (2%)
PIC Latch:       0
I/O cells:       20


Details:
CCU2D:          9
CU2:            1
FADD2B:         1
FD1P3BX:        9
FD1P3DX:        42
FD1P3IX:        8
FD1S3AX:        1
FD1S3BX:        2
FD1S3DX:        47
FD1S3IX:        3
GSR:            1
IB:             10
IFS1P3DX:       8
INV:            12
OB:             10
ORCALUT4:       254
PFUMX:          16
PUR:            1
VHI:            11
VLO:            11
false:          3
true:           3
Mapper successful!

At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 33MB peak: 171MB)

Process took 0h:00m:03s realtime, 0h:00m:03s cputime
# Sat Sep 30 04:33:38 2017

###########################################################]