#Build: Synplify Pro L-2016.03L-1, Build 097R, Jul  4 2016
#install: C:\lscc\diamond\3.8\synpbase
#OS: Windows 8 6.2
#Hostname: RORDRIGO

# Sun Sep 17 19:57:41 2017

#Implementation: proyecto_global

Synopsys HDL Compiler, version comp2016q2rc, Build 192R, built Jul  5 2016
@N: :  | Running in 64-bit mode 
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.

Synopsys VHDL Compiler, version comp2016q2rc, Build 192R, built Jul  5 2016
@N: :  | Running in 64-bit mode 
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.

@N:CD720 : std.vhd(123) | Setting time resolution to ns
@N: : control_disp.vhd(5) | Top entity is set to control_disp.
VHDL syntax check successful!

At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 69MB peak: 70MB)


Process completed successfully.
# Sun Sep 17 19:57:42 2017

###########################################################]
Synopsys Verilog Compiler, version comp2016q2rc, Build 192R, built Jul  5 2016
@N: :  | Running in 64-bit mode 
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.

@I::"C:\lscc\diamond\3.8\synpbase\lib\lucent\machxo2.v" (library work)
@I::"C:\lscc\diamond\3.8\synpbase\lib\lucent\pmi_def.v" (library work)
@I::"C:\lscc\diamond\3.8\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__)
@I::"C:\lscc\diamond\3.8\synpbase\lib\vlog\umr_capim.v" (library snps_haps)
@I::"C:\lscc\diamond\3.8\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
@I::"C:\lscc\diamond\3.8\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
@I::"C:\TFG\exp1_cont\proyecto_global\esquema_global.v" (library work)
Verilog syntax check successful!

At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 69MB peak: 70MB)


Process completed successfully.
# Sun Sep 17 19:57:42 2017

###########################################################]
@I::"C:\lscc\diamond\3.8\synpbase\lib\lucent\machxo2.v" (library work)
@I::"C:\lscc\diamond\3.8\synpbase\lib\lucent\pmi_def.v" (library work)
@I::"C:\lscc\diamond\3.8\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__)
@I::"C:\lscc\diamond\3.8\synpbase\lib\vlog\umr_capim.v" (library snps_haps)
@I::"C:\lscc\diamond\3.8\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
@I::"C:\lscc\diamond\3.8\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
@I::"C:\TFG\exp1_cont\proyecto_global\esquema_global.v" (library work)
Verilog syntax check successful!
File C:\TFG\exp1_cont\proyecto_global\esquema_global.v changed - recompiling
@N:CG364 : machxo2.v(43) | Synthesizing module AND2 in library work.

@N:CG364 : machxo2.v(563) | Synthesizing module INV in library work.

@N:CG364 : machxo2.v(56) | Synthesizing module AND4 in library work.

@N:CG364 : machxo2.v(857) | Synthesizing module OB in library work.

@N:CG364 : machxo2.v(498) | Synthesizing module IB in library work.

@N:CG364 : machxo2.v(1120) | Synthesizing module VHI in library work.

@N:CG364 : machxo2.v(1793) | Synthesizing module OSCH in library work.

@N:CG364 : esquema_global.v(3) | Synthesizing module esquema_global in library work.

@N:CG794 : esquema_global.v(66) | Using module cont_BCD from library work
@N:CG794 : esquema_global.v(69) | Using module divfrec1 from library work
@N:CG794 : esquema_global.v(96) | Using module DEC_DISP from library work

At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 70MB peak: 71MB)


Process completed successfully.
# Sun Sep 17 19:57:42 2017

###########################################################]
@N:CD720 : std.vhd(123) | Setting time resolution to ns
@N: : cont_BCD.vhd(14) | Top entity is set to cont_BCD.

File Dependency file is up to date.  It will not be rewritten.

VHDL syntax check successful!
@N:CD630 : DECODIF.vhd(4) | Synthesizing work.dec_disp.dec_disp_arch.
Post processing for work.dec_disp.dec_disp_arch
@N:CD630 : divfrec1.vhd(14) | Synthesizing work.divfrec1.structure.
Post processing for work.divfrec1.structure
@N:CD630 : cont_BCD.vhd(14) | Synthesizing work.cont_bcd.structure.
Post processing for work.cont_bcd.structure

At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 70MB peak: 71MB)


Process completed successfully.
# Sun Sep 17 19:57:42 2017

###########################################################]
Synopsys Netlist Linker, version comp2016q2rc, Build 192R, built Jul  5 2016
@N: :  | Running in 64-bit mode 
File C:\TFG\exp1_cont\proyecto_global\synwork\layer0.srs changed - recompiling
File C:\TFG\exp1_cont\proyecto_global\synwork\layer1.srs changed - recompiling
@W:Z198 : divfrec1.vhd(211) | Unbound component ROM16X1A of instance LUT4_7 
@W:Z198 : divfrec1.vhd(216) | Unbound component ROM16X1A of instance LUT4_6 
@W:Z198 : divfrec1.vhd(221) | Unbound component ROM16X1A of instance LUT4_5 
@W:Z198 : divfrec1.vhd(226) | Unbound component ROM16X1A of instance LUT4_4 
@W:Z198 : divfrec1.vhd(231) | Unbound component ROM16X1A of instance LUT4_3 
@W:Z198 : divfrec1.vhd(236) | Unbound component ROM16X1A of instance LUT4_2 
@W:Z198 : divfrec1.vhd(241) | Unbound component ROM16X1A of instance LUT4_1 
@W:Z198 : divfrec1.vhd(247) | Unbound component ROM16X1A of instance LUT4_0 
@W:Z198 : divfrec1.vhd(252) | Unbound component MUX21 of instance muxb_20 
@W:Z198 : divfrec1.vhd(256) | Unbound component MUX21 of instance muxb_19 
@W:Z198 : divfrec1.vhd(260) | Unbound component MUX21 of instance muxb_18 
@W:Z198 : divfrec1.vhd(264) | Unbound component MUX21 of instance muxb_17 
@W:Z198 : divfrec1.vhd(268) | Unbound component MUX21 of instance muxb_16 
@W:Z198 : divfrec1.vhd(272) | Unbound component MUX21 of instance muxb_15 
@W:Z198 : divfrec1.vhd(276) | Unbound component MUX21 of instance muxb_14 
@W:Z198 : divfrec1.vhd(280) | Unbound component MUX21 of instance muxb_13 
@W:Z198 : divfrec1.vhd(284) | Unbound component MUX21 of instance muxb_12 
@W:Z198 : divfrec1.vhd(288) | Unbound component MUX21 of instance muxb_11 
@W:Z198 : divfrec1.vhd(292) | Unbound component MUX21 of instance muxb_10 
@W:Z198 : divfrec1.vhd(296) | Unbound component MUX21 of instance muxb_9 
@W:Z198 : divfrec1.vhd(300) | Unbound component MUX21 of instance muxb_8 
@W:Z198 : divfrec1.vhd(304) | Unbound component MUX21 of instance muxb_7 
@W:Z198 : divfrec1.vhd(308) | Unbound component MUX21 of instance muxb_6 
@W:Z198 : divfrec1.vhd(312) | Unbound component MUX21 of instance muxb_5 
@W:Z198 : divfrec1.vhd(316) | Unbound component MUX21 of instance muxb_4 
@W:Z198 : divfrec1.vhd(320) | Unbound component MUX21 of instance muxb_3 
@W:Z198 : divfrec1.vhd(324) | Unbound component MUX21 of instance muxb_2 
@W:Z198 : divfrec1.vhd(328) | Unbound component MUX21 of instance muxb_1 
@W:Z198 : divfrec1.vhd(332) | Unbound component MUX21 of instance muxb_0 
@W:Z198 : divfrec1.vhd(336) | Unbound component FD1P3DX of instance FF_20 
@W:Z198 : divfrec1.vhd(340) | Unbound component FD1P3DX of instance FF_19 
@W:Z198 : divfrec1.vhd(344) | Unbound component FD1P3DX of instance FF_18 
@W:Z198 : divfrec1.vhd(348) | Unbound component FD1P3DX of instance FF_17 
@W:Z198 : divfrec1.vhd(352) | Unbound component FD1P3DX of instance FF_16 
@W:Z198 : divfrec1.vhd(356) | Unbound component FD1P3DX of instance FF_15 
@W:Z198 : divfrec1.vhd(360) | Unbound component FD1P3DX of instance FF_14 
@W:Z198 : divfrec1.vhd(364) | Unbound component FD1P3DX of instance FF_13 
@W:Z198 : divfrec1.vhd(368) | Unbound component FD1P3DX of instance FF_12 
@W:Z198 : divfrec1.vhd(372) | Unbound component FD1P3DX of instance FF_11 
@W:Z198 : divfrec1.vhd(376) | Unbound component FD1P3DX of instance FF_10 
@W:Z198 : divfrec1.vhd(380) | Unbound component FD1P3DX of instance FF_9 
@W:Z198 : divfrec1.vhd(384) | Unbound component FD1P3DX of instance FF_8 
@W:Z198 : divfrec1.vhd(388) | Unbound component FD1P3DX of instance FF_7 
@W:Z198 : divfrec1.vhd(392) | Unbound component FD1P3DX of instance FF_6 
@W:Z198 : divfrec1.vhd(396) | Unbound component FD1P3DX of instance FF_5 
@W:Z198 : divfrec1.vhd(400) | Unbound component FD1P3DX of instance FF_4 
@W:Z198 : divfrec1.vhd(404) | Unbound component FD1P3DX of instance FF_3 
@W:Z198 : divfrec1.vhd(408) | Unbound component FD1P3DX of instance FF_2 
@W:Z198 : divfrec1.vhd(412) | Unbound component FD1P3DX of instance FF_1 
@W:Z198 : divfrec1.vhd(416) | Unbound component FD1P3DX of instance FF_0 
@W:Z198 : divfrec1.vhd(423) | Unbound component FADD2B of instance cnt_cia 
@W:Z198 : divfrec1.vhd(428) | Unbound component CU2 of instance cnt_0 
@W:Z198 : divfrec1.vhd(432) | Unbound component CU2 of instance cnt_1 
@W:Z198 : divfrec1.vhd(436) | Unbound component CU2 of instance cnt_2 
@W:Z198 : divfrec1.vhd(440) | Unbound component CU2 of instance cnt_3 
@W:Z198 : divfrec1.vhd(444) | Unbound component CU2 of instance cnt_4 
@W:Z198 : divfrec1.vhd(448) | Unbound component CU2 of instance cnt_5 
@W:Z198 : divfrec1.vhd(452) | Unbound component CU2 of instance cnt_6 
@W:Z198 : divfrec1.vhd(456) | Unbound component CU2 of instance cnt_7 
@W:Z198 : divfrec1.vhd(460) | Unbound component CU2 of instance cnt_8 
@W:Z198 : divfrec1.vhd(464) | Unbound component CU2 of instance cnt_9 
@W:Z198 : divfrec1.vhd(468) | Unbound component CU2 of instance cnt_10 
@W:Z198 : divfrec1.vhd(472) | Unbound component VLO of instance scuba_vlo_inst 
@W:Z198 : cont_BCD.vhd(95) | Unbound component ROM16X1A of instance LUT4_0 
@W:Z198 : cont_BCD.vhd(100) | Unbound component MUX21 of instance muxb_3 
@W:Z198 : cont_BCD.vhd(104) | Unbound component MUX21 of instance muxb_2 
@W:Z198 : cont_BCD.vhd(108) | Unbound component MUX21 of instance muxb_1 
@W:Z198 : cont_BCD.vhd(112) | Unbound component MUX21 of instance muxb_0 
@W:Z198 : cont_BCD.vhd(116) | Unbound component FD1P3DX of instance FF_3 
@W:Z198 : cont_BCD.vhd(120) | Unbound component FD1P3DX of instance FF_2 
@W:Z198 : cont_BCD.vhd(124) | Unbound component FD1P3DX of instance FF_1 
@W:Z198 : cont_BCD.vhd(128) | Unbound component FD1P3DX of instance FF_0 
@W:Z198 : cont_BCD.vhd(132) | Unbound component VLO of instance scuba_vlo_inst 
@W:Z198 : cont_BCD.vhd(138) | Unbound component FADD2B of instance cnt_cia 
@W:Z198 : cont_BCD.vhd(143) | Unbound component CU2 of instance cnt_0 
@W:Z198 : cont_BCD.vhd(147) | Unbound component CU2 of instance cnt_1 

=======================================================================================
For a summary of linker messages for components that did not bind, please see log file:
Linked File: proyecto_global_proyecto_global_comp.linkerlog
=======================================================================================


At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Sun Sep 17 19:57:43 2017

###########################################################]
@END

At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Sun Sep 17 19:57:43 2017

###########################################################]
Synopsys Netlist Linker, version comp2016q2rc, Build 192R, built Jul  5 2016
@N: :  | Running in 64-bit mode 
File C:\TFG\exp1_cont\proyecto_global\synwork\proyecto_global_proyecto_global_comp.srs changed - recompiling

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Sun Sep 17 19:57:44 2017

###########################################################]
Pre-mapping Report

Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1498R, Built Jul  5 2016 10:30:31
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
Product Version L-2016.03L-1

Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)

@A:MF827 :  | No constraint file specified. 
Linked File: proyecto_global_proyecto_global_scck.rpt
Printing clock  summary report in "C:\TFG\exp1_cont\proyecto_global\proyecto_global_proyecto_global_scck.rpt" file 
@N:MF248 :  | Running in 64-bit mode. 
@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 112MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 114MB)

ICG Latch Removal Summary:
Number of ICG latches removed:	0
Number of ICG latches not removed:	0
syn_allowed_resources : blockrams=7  set on top level netlist esquema_global

Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)



Clock Summary
*****************

Start                                  Requested     Requested     Clock                                                 Clock                   Clock
Clock                                  Frequency     Period        Type                                                  Group                   Load 
------------------------------------------------------------------------------------------------------------------------------------------------------
System                                 1.0 MHz       1000.000      system                                                system_clkgroup         0    
divfrec1|tdataout20_derived_clock      2.1 MHz       480.769       derived (from esquema_global|N_25_inferred_clock)     Inferred_clkgroup_0     12   
esquema_global|N_25_inferred_clock     2.1 MHz       480.769       inferred                                              Inferred_clkgroup_0     21   
======================================================================================================================================================

@W:MT529 : divfrec1.vhd(336) | Found inferred clock esquema_global|N_25_inferred_clock which controls 21 sequential elements including I7.FF_20. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 

Finished Pre Mapping Phase.

Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)

None
None

Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)

Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 141MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Sun Sep 17 19:57:45 2017

###########################################################]
Map & Optimize Report

Synopsys Lattice Technology Mapper, Version maplat, Build 1498R, Built Jul  5 2016 10:30:31
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
Product Version L-2016.03L-1

Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)

@N:MF248 :  | Running in 64-bit mode. 
@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 111MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 113MB)



Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)


Available hyper_sources - for debug and ip models
	None Found

@W:FA239 : decodif.vhd(25) | ROM I23.SEGMENTOS_1[6:0] (in view: work.esquema_global(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@W:FA239 : decodif.vhd(25) | ROM I35.SEGMENTOS_1[6:0] (in view: work.esquema_global(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@W:FA239 : decodif.vhd(25) | ROM I23.SEGMENTOS_1[6:0] (in view: work.esquema_global(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@N:MO106 : decodif.vhd(25) | Found ROM .delname. (in view: work.esquema_global(verilog)) with 10 words by 7 bits.
@W:FA239 : decodif.vhd(25) | ROM I35.SEGMENTOS_1[6:0] (in view: work.esquema_global(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@N:MO106 : decodif.vhd(25) | Found ROM .delname. (in view: work.esquema_global(verilog)) with 10 words by 7 bits.

Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)


Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)


Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 141MB)


Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)


Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)


Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)


Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)


Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)


Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)


Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:00s		   475.80ns		  14 /         0

Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)

@N:FX164 :  | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.   

Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)



@S |Clock Optimization Summary


#### START OF CLOCK OPTIMIZATION REPORT #####[

1 non-gated/non-generated clock tree(s) driving 12 clock pin(s) of sequential element(s)
1 gated/generated clock tree(s) driving 21 clock pin(s) of sequential element(s)
0 instances converted, 21 sequential instances remain driven by gated/generated clocks

=========================== Non-Gated/Non-Generated Clocks ============================
Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
---------------------------------------------------------------------------------------
ClockId0002        I7.FF_0             FD1P3DX                12         I43.FF_0       
=======================================================================================
================================================================ Gated/Generated Clocks =================================================================
Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance     Explanation                                                  
---------------------------------------------------------------------------------------------------------------------------------------------------------
ClockId0001        I5                  OSCH                   21         I7.FF_0             No gated clock conversion method for cell cell:LUCENT.FD1P3DX
=========================================================================================================================================================


##### END OF CLOCK OPTIMIZATION REPORT ######]


Start Writing Netlists (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 106MB peak: 141MB)

Writing Analyst data base C:\TFG\exp1_cont\proyecto_global\synwork\proyecto_global_proyecto_global_m.srm

Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 141MB)

Writing EDIF Netlist and constraint files
@N:FX1056 :  | Writing EDF file: C:\TFG\exp1_cont\proyecto_global\proyecto_global_proyecto_global.edi 
L-2016.03L-1
@N:BW106 :  | Synplicity Constraint File capacitance units using default value of 1pF  

Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 142MB peak: 144MB)


Start final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 144MB)

@W:MT246 : esquema_global.v(65) | Blackbox AND4 is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@W:MT420 :  | Found inferred clock esquema_global|N_25_inferred_clock with period 480.77ns. Please declare a user-defined clock on object "n:N_25" 
@N:MT615 :  | Found clock divfrec1|tdataout20_derived_clock with period 480.77ns  


##### START OF TIMING REPORT #####[
# Timing Report written on Sun Sep 17 19:57:47 2017
#


Top view:               esquema_global
Requested Frequency:    2.1 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    
@N:MT320 :  | Timing report estimates place and route data. Please look at the place and route timing report for final timing. 

@N:MT322 :  | Clock constraints cover only FF-to-FF paths associated with the clock. 



Performance Summary
*******************


Worst slack in design: 475.795

@N:MT286 :  | System clock period 0.000 stretches to negative invalid value -- ignoring stretching. 
                                       Requested     Estimated     Requested     Estimated                 Clock                                                 Clock              
Starting Clock                         Frequency     Frequency     Period        Period        Slack       Type                                                  Group              
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
divfrec1|tdataout20_derived_clock      2.1 MHz       334.2 MHz     480.769       2.993         477.777     derived (from esquema_global|N_25_inferred_clock)     Inferred_clkgroup_0
esquema_global|N_25_inferred_clock     2.1 MHz       201.0 MHz     480.769       4.974         475.795     inferred                                              Inferred_clkgroup_0
System                                 1.0 MHz       1.9 MHz       1000.000      519.702       480.298     system                                                system_clkgroup    
====================================================================================================================================================================================





Clock Relationships
*******************

Clocks                                                                  |    rise  to  rise      |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
-----------------------------------------------------------------------------------------------------------------------------------------------------------------
Starting                            Ending                              |  constraint  slack     |  constraint  slack  |  constraint  slack  |  constraint  slack
-----------------------------------------------------------------------------------------------------------------------------------------------------------------
System                              System                              |  1000.000    1000.000  |  No paths    -      |  No paths    -      |  No paths    -    
System                              esquema_global|N_25_inferred_clock  |  480.769     480.664   |  No paths    -      |  No paths    -      |  No paths    -    
System                              divfrec1|tdataout20_derived_clock   |  480.769     480.298   |  No paths    -      |  No paths    -      |  No paths    -    
esquema_global|N_25_inferred_clock  System                              |  480.769     475.795   |  No paths    -      |  No paths    -      |  No paths    -    
divfrec1|tdataout20_derived_clock   System                              |  480.769     477.777   |  No paths    -      |  No paths    -      |  No paths    -    
=================================================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

No IO constraint found



====================================
Detailed Report for Clock: divfrec1|tdataout20_derived_clock
====================================



Starting Points with Worst Slack
********************************

             Starting                                                            Arrival            
Instance     Reference                             Type        Pin     Net       Time        Slack  
             Clock                                                                                  
----------------------------------------------------------------------------------------------------
I8.FF_1      divfrec1|tdataout20_derived_clock     FD1P3DX     Q       SL[2]     1.232       477.777
I8.FF_2      divfrec1|tdataout20_derived_clock     FD1P3DX     Q       SL[1]     1.232       477.777
I27.FF_1     divfrec1|tdataout20_derived_clock     FD1P3DX     Q       R[2]      1.228       477.781
I27.FF_2     divfrec1|tdataout20_derived_clock     FD1P3DX     Q       R[1]      1.228       477.781
I43.FF_1     divfrec1|tdataout20_derived_clock     FD1P3DX     Q       ST[2]     1.148       477.861
I43.FF_2     divfrec1|tdataout20_derived_clock     FD1P3DX     Q       ST[1]     1.148       477.861
I8.FF_0      divfrec1|tdataout20_derived_clock     FD1P3DX     Q       SL[3]     1.232       478.345
I8.FF_3      divfrec1|tdataout20_derived_clock     FD1P3DX     Q       SL[0]     1.232       478.345
I27.FF_0     divfrec1|tdataout20_derived_clock     FD1P3DX     Q       R[3]      1.228       478.349
I27.FF_3     divfrec1|tdataout20_derived_clock     FD1P3DX     Q       R[0]      1.228       478.349
====================================================================================================


Ending Points with Worst Slack
******************************

               Starting                                                             Required            
Instance       Reference                             Type      Pin     Net          Time         Slack  
               Clock                                                                                    
--------------------------------------------------------------------------------------------------------
I8.muxb_0      divfrec1|tdataout20_derived_clock     MUX21     SD      dec0_sr9     480.769      477.777
I8.muxb_1      divfrec1|tdataout20_derived_clock     MUX21     SD      dec0_sr9     480.769      477.777
I8.muxb_2      divfrec1|tdataout20_derived_clock     MUX21     SD      dec0_sr9     480.769      477.777
I8.muxb_3      divfrec1|tdataout20_derived_clock     MUX21     SD      dec0_sr9     480.769      477.777
I27.muxb_0     divfrec1|tdataout20_derived_clock     MUX21     SD      dec0_sr9     480.769      477.781
I27.muxb_1     divfrec1|tdataout20_derived_clock     MUX21     SD      dec0_sr9     480.769      477.781
I27.muxb_2     divfrec1|tdataout20_derived_clock     MUX21     SD      dec0_sr9     480.769      477.781
I27.muxb_3     divfrec1|tdataout20_derived_clock     MUX21     SD      dec0_sr9     480.769      477.781
I43.muxb_0     divfrec1|tdataout20_derived_clock     MUX21     SD      dec0_sr9     480.769      477.861
I43.muxb_1     divfrec1|tdataout20_derived_clock     MUX21     SD      dec0_sr9     480.769      477.861
========================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      480.769
    - Setup time:                            0.000
    + Clock delay at ending point:           0.000 (ideal)
    + Estimated clock delay at ending point: 0.000
    = Required time:                         480.769

    - Propagation time:                      2.993
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 477.777

    Number of logic level(s):                2
    Starting point:                          I8.FF_1 / Q
    Ending point:                            I8.muxb_0 / SD
    The start point is clocked by            divfrec1|tdataout20_derived_clock [rising] on pin CK
    The end   point is clocked by            System [rising]

Instance / Net                  Pin      Pin               Arrival     No. of    
Name               Type         Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------
I8.FF_1            FD1P3DX      Q        Out     1.232     1.232       -         
SL[2]              Net          -        -       -         -           10        
I8.INV_0           INV          A        In      0.000     1.232       -         
I8.INV_0           INV          Z        Out     0.568     1.800       -         
tdataout2_inv      Net          -        -       -         -           1         
I8.LUT4_0          ROM16X1A     AD1      In      0.000     1.800       -         
I8.LUT4_0          ROM16X1A     DO0      Out     1.193     2.993       -         
dec0_sr9           Net          -        -       -         -           4         
I8.muxb_0          MUX21        SD       In      0.000     2.993       -         
=================================================================================




====================================
Detailed Report for Clock: esquema_global|N_25_inferred_clock
====================================



Starting Points with Worst Slack
********************************

             Starting                                                             Arrival            
Instance     Reference                              Type        Pin     Net       Time        Slack  
             Clock                                                                                   
-----------------------------------------------------------------------------------------------------
I7.FF_6      esquema_global|N_25_inferred_clock     FD1P3DX     Q       Q[14]     1.044       475.795
I7.FF_11     esquema_global|N_25_inferred_clock     FD1P3DX     Q       Q[9]      1.044       475.795
I7.FF_13     esquema_global|N_25_inferred_clock     FD1P3DX     Q       Q[7]      1.044       475.795
I7.FF_14     esquema_global|N_25_inferred_clock     FD1P3DX     Q       Q[6]      1.044       475.795
I7.FF_15     esquema_global|N_25_inferred_clock     FD1P3DX     Q       Q[5]      1.044       475.795
I7.FF_16     esquema_global|N_25_inferred_clock     FD1P3DX     Q       Q[4]      1.044       475.795
I7.FF_17     esquema_global|N_25_inferred_clock     FD1P3DX     Q       Q[3]      1.044       475.795
I7.FF_18     esquema_global|N_25_inferred_clock     FD1P3DX     Q       Q[2]      1.044       475.795
I7.FF_19     esquema_global|N_25_inferred_clock     FD1P3DX     Q       Q[1]      1.044       475.795
I7.FF_20     esquema_global|N_25_inferred_clock     FD1P3DX     Q       Q[0]      1.044       475.795
=====================================================================================================


Ending Points with Worst Slack
******************************

              Starting                                                                   Required            
Instance      Reference                              Type      Pin     Net               Time         Slack  
              Clock                                                                                          
-------------------------------------------------------------------------------------------------------------
I7.muxb_0     esquema_global|N_25_inferred_clock     MUX21     SD      dec0_sr1fbd00     480.769      475.795
I7.muxb_1     esquema_global|N_25_inferred_clock     MUX21     SD      dec0_sr1fbd00     480.769      475.795
I7.muxb_2     esquema_global|N_25_inferred_clock     MUX21     SD      dec0_sr1fbd00     480.769      475.795
I7.muxb_3     esquema_global|N_25_inferred_clock     MUX21     SD      dec0_sr1fbd00     480.769      475.795
I7.muxb_4     esquema_global|N_25_inferred_clock     MUX21     SD      dec0_sr1fbd00     480.769      475.795
I7.muxb_5     esquema_global|N_25_inferred_clock     MUX21     SD      dec0_sr1fbd00     480.769      475.795
I7.muxb_6     esquema_global|N_25_inferred_clock     MUX21     SD      dec0_sr1fbd00     480.769      475.795
I7.muxb_7     esquema_global|N_25_inferred_clock     MUX21     SD      dec0_sr1fbd00     480.769      475.795
I7.muxb_8     esquema_global|N_25_inferred_clock     MUX21     SD      dec0_sr1fbd00     480.769      475.795
I7.muxb_9     esquema_global|N_25_inferred_clock     MUX21     SD      dec0_sr1fbd00     480.769      475.795
=============================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      480.769
    - Setup time:                            0.000
    + Clock delay at ending point:           0.000 (ideal)
    + Estimated clock delay at ending point: 0.000
    = Required time:                         480.769

    - Propagation time:                      4.974
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     475.795

    Number of logic level(s):                4
    Starting point:                          I7.FF_6 / Q
    Ending point:                            I7.muxb_0 / SD
    The start point is clocked by            esquema_global|N_25_inferred_clock [rising] on pin CK
    The end   point is clocked by            System [rising]

Instance / Net                   Pin      Pin               Arrival     No. of    
Name                Type         Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------
I7.FF_6             FD1P3DX      Q        Out     1.044     1.044       -         
Q[14]               Net          -        -       -         -           2         
I7.INV_0            INV          A        In      0.000     1.044       -         
I7.INV_0            INV          Z        Out     0.568     1.612       -         
tdataout14_inv      Net          -        -       -         -           1         
I7.LUT4_4           ROM16X1A     AD1      In      0.000     1.612       -         
I7.LUT4_4           ROM16X1A     DO0      Out     1.017     2.629       -         
func_and_inet_3     Net          -        -       -         -           1         
I7.LUT4_1           ROM16X1A     AD0      In      0.000     2.629       -         
I7.LUT4_1           ROM16X1A     DO0      Out     1.017     3.645       -         
func_and_inet_6     Net          -        -       -         -           1         
I7.LUT4_0           ROM16X1A     AD3      In      0.000     3.645       -         
I7.LUT4_0           ROM16X1A     DO0      Out     1.329     4.974       -         
dec0_sr1fbd00       Net          -        -       -         -           21        
I7.muxb_0           MUX21        SD       In      0.000     4.974       -         
==================================================================================




====================================
Detailed Report for Clock: System
====================================



Starting Points with Worst Slack
********************************

               Starting                                       Arrival            
Instance       Reference     Type      Pin     Net            Time        Slack  
               Clock                                                             
---------------------------------------------------------------------------------
I42            System        AND4      Z       N_14           0.000       480.298
I49            System        AND2      Z       N_7            0.000       480.298
I7.muxb_0      System        MUX21     Z       ldataout20     0.000       480.664
I43.muxb_0     System        MUX21     Z       ldataout3      0.000       480.664
I27.muxb_0     System        MUX21     Z       ldataout3      0.000       480.664
I8.muxb_0      System        MUX21     Z       ldataout3      0.000       480.664
I43.muxb_1     System        MUX21     Z       ldataout2      0.000       480.664
I27.muxb_1     System        MUX21     Z       ldataout2      0.000       480.664
I8.muxb_1      System        MUX21     Z       ldataout2      0.000       480.664
I7.muxb_1      System        MUX21     Z       ldataout19     0.000       480.664
=================================================================================


Ending Points with Worst Slack
******************************

             Starting                                         Required            
Instance     Reference     Type        Pin     Net            Time         Slack  
             Clock                                                                
----------------------------------------------------------------------------------
I27.FF_0     System        FD1P3DX     SP      N_7            480.298      480.298
I8.FF_0      System        FD1P3DX     SP      N_14           480.298      480.298
I8.FF_1      System        FD1P3DX     SP      N_14           480.298      480.298
I27.FF_1     System        FD1P3DX     SP      N_7            480.298      480.298
I27.FF_2     System        FD1P3DX     SP      N_7            480.298      480.298
I8.FF_2      System        FD1P3DX     SP      N_14           480.298      480.298
I8.FF_3      System        FD1P3DX     SP      N_14           480.298      480.298
I27.FF_3     System        FD1P3DX     SP      N_7            480.298      480.298
I43.FF_0     System        FD1P3DX     D       ldataout3      480.664      480.664
I7.FF_0      System        FD1P3DX     D       ldataout20     480.664      480.664
==================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      480.769
    - Setup time:                            0.472
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         480.298

    - Propagation time:                      0.000
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 480.298

    Number of logic level(s):                0
    Starting point:                          I42 / Z
    Ending point:                            I8.FF_0 / SP
    The start point is clocked by            System [rising]
    The end   point is clocked by            divfrec1|tdataout20_derived_clock [rising] on pin CK

Instance / Net                 Pin      Pin               Arrival     No. of    
Name               Type        Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------
I42                AND4        Z        Out     0.000     0.000       -         
N_14               Net         -        -       -         -           5         
I8.FF_0            FD1P3DX     SP       In      0.000     0.000       -         
================================================================================



##### END OF TIMING REPORT #####]

Constraints that could not be applied
None

Finished final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 144MB)


Finished timing report (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 144MB)

---------------------------------------
Resource Usage Report
Part: lcmxo2_1200ze-1

Register bits: 33 of 1280 (3%)
PIC Latch:       0
I/O cells:       22


Details:
AND2:           1
AND4:           2
CU2:            17
FADD2B:         4
FD1P3DX:        33
GSR:            1
IB:             3
INV:            24
MUX21:          33
OB:             19
ORCALUT4:       14
OSCH:           1
PUR:            1
ROM16X1A:       11
VHI:            5
VLO:            5
false:          2
true:           2
Mapper successful!

At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 30MB peak: 144MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Sun Sep 17 19:57:47 2017

###########################################################]