Setting log file to 'C:/TFG/exp6_2/proyecto_global/hdla_gen_hierarchy.html'. Starting: parse design source files (VHDL-1481) Analyzing VHDL file C:/lscc/diamond/3.8/ispfpga/vhdl_packages/standard.vhd INFO - C:/lscc/diamond/3.8/ispfpga/vhdl_packages/standard.vhd(9,9-9,17) (VHDL-1014) analyzing package standard (VHDL-1481) Analyzing VHDL file C:/lscc/diamond/3.8/ispfpga/vhdl_packages/std_1164.vhd INFO - C:/lscc/diamond/3.8/ispfpga/vhdl_packages/std_1164.vhd(15,9-15,23) (VHDL-1014) analyzing package std_logic_1164 INFO - C:/lscc/diamond/3.8/ispfpga/vhdl_packages/std_1164.vhd(178,14-178,28) (VHDL-1013) analyzing package body std_logic_1164 (VHDL-1481) Analyzing VHDL file C:/lscc/diamond/3.8/ispfpga/vhdl_packages/mgc_qsim.vhd INFO - C:/lscc/diamond/3.8/ispfpga/vhdl_packages/mgc_qsim.vhd(18,9-18,19) (VHDL-1014) analyzing package qsim_logic INFO - C:/lscc/diamond/3.8/ispfpga/vhdl_packages/mgc_qsim.vhd(753,14-753,24) (VHDL-1013) analyzing package body qsim_logic (VHDL-1481) Analyzing VHDL file C:/lscc/diamond/3.8/ispfpga/vhdl_packages/numeric_bit.vhd INFO - C:/lscc/diamond/3.8/ispfpga/vhdl_packages/numeric_bit.vhd(54,9-54,20) (VHDL-1014) analyzing package numeric_bit INFO - C:/lscc/diamond/3.8/ispfpga/vhdl_packages/numeric_bit.vhd(834,14-834,25) (VHDL-1013) analyzing package body numeric_bit (VHDL-1481) Analyzing VHDL file C:/lscc/diamond/3.8/ispfpga/vhdl_packages/numeric_std.vhd INFO - C:/lscc/diamond/3.8/ispfpga/vhdl_packages/numeric_std.vhd(57,9-57,20) (VHDL-1014) analyzing package numeric_std INFO - C:/lscc/diamond/3.8/ispfpga/vhdl_packages/numeric_std.vhd(874,14-874,25) (VHDL-1013) analyzing package body numeric_std (VHDL-1481) Analyzing VHDL file C:/lscc/diamond/3.8/ispfpga/vhdl_packages/textio.vhd INFO - C:/lscc/diamond/3.8/ispfpga/vhdl_packages/textio.vhd(13,9-13,15) (VHDL-1014) analyzing package textio INFO - C:/lscc/diamond/3.8/ispfpga/vhdl_packages/textio.vhd(114,14-114,20) (VHDL-1013) analyzing package body textio (VHDL-1481) Analyzing VHDL file C:/lscc/diamond/3.8/ispfpga/vhdl_packages/std_logic_textio.vhd INFO - C:/lscc/diamond/3.8/ispfpga/vhdl_packages/std_logic_textio.vhd(26,9-26,25) (VHDL-1014) analyzing package std_logic_textio INFO - C:/lscc/diamond/3.8/ispfpga/vhdl_packages/std_logic_textio.vhd(72,14-72,30) (VHDL-1013) analyzing package body std_logic_textio (VHDL-1481) Analyzing VHDL file C:/lscc/diamond/3.8/ispfpga/vhdl_packages/syn_attr.vhd INFO - C:/lscc/diamond/3.8/ispfpga/vhdl_packages/syn_attr.vhd(39,9-39,19) (VHDL-1014) analyzing package attributes (VHDL-1481) Analyzing VHDL file C:/lscc/diamond/3.8/ispfpga/vhdl_packages/syn_misc.vhd INFO - C:/lscc/diamond/3.8/ispfpga/vhdl_packages/syn_misc.vhd(30,9-30,23) (VHDL-1014) analyzing package std_logic_misc INFO - C:/lscc/diamond/3.8/ispfpga/vhdl_packages/syn_misc.vhd(182,14-182,28) (VHDL-1013) analyzing package body std_logic_misc INFO - ./.__tmp_vxr_0_(56,9-56,18) (VHDL-1014) analyzing package math_real INFO - ./.__tmp_vxr_0_(685,14-685,23) (VHDL-1013) analyzing package body math_real (VHDL-1481) Analyzing VHDL file C:/lscc/diamond/3.8/ispfpga/vhdl_packages/mixed_lang_vltype.vhd INFO - C:/lscc/diamond/3.8/ispfpga/vhdl_packages/mixed_lang_vltype.vhd(9,9-9,17) (VHDL-1014) analyzing package vl_types INFO - C:/lscc/diamond/3.8/ispfpga/vhdl_packages/mixed_lang_vltype.vhd(88,14-88,22) (VHDL-1013) analyzing package body vl_types (VHDL-1481) Analyzing VHDL file C:/lscc/diamond/3.8/ispfpga/vhdl_packages/syn_arit.vhd INFO - C:/lscc/diamond/3.8/ispfpga/vhdl_packages/syn_arit.vhd(25,9-25,24) (VHDL-1014) analyzing package std_logic_arith INFO - C:/lscc/diamond/3.8/ispfpga/vhdl_packages/syn_arit.vhd(206,14-206,29) (VHDL-1013) analyzing package body std_logic_arith (VHDL-1481) Analyzing VHDL file C:/lscc/diamond/3.8/ispfpga/vhdl_packages/syn_sign.vhd INFO - C:/lscc/diamond/3.8/ispfpga/vhdl_packages/syn_sign.vhd(35,9-35,25) (VHDL-1014) analyzing package std_logic_signed INFO - C:/lscc/diamond/3.8/ispfpga/vhdl_packages/syn_sign.vhd(96,14-96,30) (VHDL-1013) analyzing package body std_logic_signed (VHDL-1481) Analyzing VHDL file C:/lscc/diamond/3.8/ispfpga/vhdl_packages/syn_unsi.vhd INFO - C:/lscc/diamond/3.8/ispfpga/vhdl_packages/syn_unsi.vhd(35,9-35,27) (VHDL-1014) analyzing package std_logic_unsigned INFO - C:/lscc/diamond/3.8/ispfpga/vhdl_packages/syn_unsi.vhd(94,14-94,32) (VHDL-1013) analyzing package body std_logic_unsigned (VHDL-1481) Analyzing VHDL file C:/lscc/diamond/3.8/ispfpga/vhdl_packages/synattr.vhd INFO - C:/lscc/diamond/3.8/ispfpga/vhdl_packages/synattr.vhd(50,9-50,19) (VHDL-1014) analyzing package attributes (VERI-1482) Analyzing Verilog file C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v (VERI-1482) Analyzing Verilog file C:/TFG/exp6_2/proyecto_global/esquema_global.v (VERI-1482) Analyzing Verilog file C:/TFG/exp6_2/dos_gpio/soc/dos_gpio.v INFO - C:/TFG/exp6_2/dos_gpio/soc/dos_gpio.v(46,10-46,25) (VERI-1328) analyzing included file C:/TFG/exp6_2/dos_gpio/soc/system_conf.v INFO - C:/TFG/exp6_2/dos_gpio/soc/dos_gpio.v(327,10-327,59) (VERI-1328) analyzing included file C:/TFG/exp6_2/dos_gpio/soc/../components/lm8/rtl/verilog/lm8_include_all.v INFO - C:/TFG/exp6_2/dos_gpio/soc/../components/lm8/rtl/verilog/lm8_include_all.v(48,10-48,21) (VERI-1328) analyzing included file C:/TFG/exp6_2/dos_gpio/soc/pmi_def.v INFO - C:/TFG/exp6_2/dos_gpio/soc/../components/lm8/rtl/verilog/lm8_include_all.v(50,10-50,25) (VERI-1328) analyzing included file C:/TFG/exp6_2/dos_gpio/soc/system_conf.v INFO - C:/TFG/exp6_2/dos_gpio/soc/../components/lm8/rtl/verilog/lm8_include_all.v(51,10-51,55) (VERI-1328) analyzing included file C:/TFG/exp6_2/dos_gpio/soc/../components/lm8/rtl/verilog/lm8_include.v INFO - C:/TFG/exp6_2/dos_gpio/soc/../components/lm8/rtl/verilog/lm8_include_all.v(52,10-52,57) (VERI-1328) analyzing included file C:/TFG/exp6_2/dos_gpio/soc/../components/lm8/rtl/verilog/lm8_interrupt.v INFO - C:/TFG/exp6_2/dos_gpio/soc/../components/lm8/rtl/verilog/lm8_interrupt.v(47,10-47,25) (VERI-1328) analyzing included file C:/TFG/exp6_2/dos_gpio/soc/system_conf.v INFO - C:/TFG/exp6_2/dos_gpio/soc/../components/lm8/rtl/verilog/lm8_include_all.v(53,10-53,55) (VERI-1328) analyzing included file C:/TFG/exp6_2/dos_gpio/soc/../components/lm8/rtl/verilog/lm8_io_cntl.v INFO - C:/TFG/exp6_2/dos_gpio/soc/../components/lm8/rtl/verilog/lm8_include_all.v(54,10-54,57) (VERI-1328) analyzing included file C:/TFG/exp6_2/dos_gpio/soc/../components/lm8/rtl/verilog/lm8_flow_cntl.v INFO - C:/TFG/exp6_2/dos_gpio/soc/../components/lm8/rtl/verilog/lm8_include_all.v(55,10-55,52) (VERI-1328) analyzing included file C:/TFG/exp6_2/dos_gpio/soc/../components/lm8/rtl/verilog/lm8_idec.v INFO - C:/TFG/exp6_2/dos_gpio/soc/../components/lm8/rtl/verilog/lm8_include_all.v(56,10-56,51) (VERI-1328) analyzing included file C:/TFG/exp6_2/dos_gpio/soc/../components/lm8/rtl/verilog/lm8_alu.v INFO - C:/TFG/exp6_2/dos_gpio/soc/../components/lm8/rtl/verilog/lm8_include_all.v(57,10-57,52) (VERI-1328) analyzing included file C:/TFG/exp6_2/dos_gpio/soc/../components/lm8/rtl/verilog/lm8_core.v WARNING - C:/TFG/exp6_2/dos_gpio/soc/../components/lm8/rtl/verilog/lm8_core.v(82,4-82,47) (VERI-1199) parameter declaration becomes local in lm8_core with formal parameter declaration list WARNING - C:/TFG/exp6_2/dos_gpio/soc/../components/lm8/rtl/verilog/lm8_core.v(83,4-83,47) (VERI-1199) parameter declaration becomes local in lm8_core with formal parameter declaration list WARNING - C:/TFG/exp6_2/dos_gpio/soc/../components/lm8/rtl/verilog/lm8_core.v(84,4-84,47) (VERI-1199) parameter declaration becomes local in lm8_core with formal parameter declaration list INFO - C:/TFG/exp6_2/dos_gpio/soc/../components/lm8/rtl/verilog/lm8_include_all.v(58,10-58,51) (VERI-1328) analyzing included file C:/TFG/exp6_2/dos_gpio/soc/../components/lm8/rtl/verilog/lm8_top.v WARNING - C:/TFG/exp6_2/dos_gpio/soc/../components/lm8/rtl/verilog/lm8_top.v(113,4-113,90) (VERI-1199) parameter declaration becomes local in lm8 with formal parameter declaration list WARNING - C:/TFG/exp6_2/dos_gpio/soc/../components/lm8/rtl/verilog/lm8_top.v(114,4-114,96) (VERI-1199) parameter declaration becomes local in lm8 with formal parameter declaration list INFO - C:/TFG/exp6_2/dos_gpio/soc/dos_gpio.v(328,10-328,49) (VERI-1328) analyzing included file C:/TFG/exp6_2/dos_gpio/soc/../components/gpio/rtl/verilog/gpio.v INFO - C:/TFG/exp6_2/dos_gpio/soc/../components/gpio/rtl/verilog/gpio.v(79,10-79,25) (VERI-1328) analyzing included file C:/TFG/exp6_2/dos_gpio/soc/system_conf.v WARNING - C:/TFG/exp6_2/dos_gpio/soc/../components/gpio/rtl/verilog/gpio.v(176,4-176,23) (VERI-1199) parameter declaration becomes local in gpio with formal parameter declaration list INFO - C:/TFG/exp6_2/dos_gpio/soc/dos_gpio.v(329,10-329,49) (VERI-1328) analyzing included file C:/TFG/exp6_2/dos_gpio/soc/../components/gpio/rtl/verilog/tpio.v INFO - C:/TFG/exp6_2/dos_gpio/soc/../components/gpio/rtl/verilog/tpio.v(65,10-65,25) (VERI-1328) analyzing included file C:/TFG/exp6_2/dos_gpio/soc/system_conf.v WARNING - C:/TFG/exp6_2/dos_gpio/soc/../components/gpio/rtl/verilog/tpio.v(87,4-87,23) (VERI-1199) parameter declaration becomes local in tpio with formal parameter declaration list (VHDL-1481) Analyzing VHDL file C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.vhd (VHDL-1481) Analyzing VHDL file C:/TFG/exp6_2/divfrec1.vhd INFO - C:/TFG/exp6_2/divfrec1.vhd(14,8-14,16) (VHDL-1012) analyzing entity divfrec1 INFO - C:/TFG/exp6_2/divfrec1.vhd(22,14-22,23) (VHDL-1010) analyzing architecture structure (VHDL-1481) Analyzing VHDL file C:/TFG/exp6_2/cont_BCD.vhd INFO - C:/TFG/exp6_2/cont_BCD.vhd(14,8-14,16) (VHDL-1012) analyzing entity cont_bcd INFO - C:/TFG/exp6_2/cont_BCD.vhd(22,14-22,23) (VHDL-1010) analyzing architecture structure (VHDL-1481) Analyzing VHDL file C:/TFG/exp6_2/DECODIF.vhd INFO - C:/TFG/exp6_2/DECODIF.vhd(4,8-4,16) (VHDL-1012) analyzing entity dec_disp INFO - C:/TFG/exp6_2/DECODIF.vhd(8,14-8,27) (VHDL-1010) analyzing architecture dec_disp_arch (VHDL-1481) Analyzing VHDL file C:/TFG/exp6_2/cont_disp.vhd INFO - C:/TFG/exp6_2/cont_disp.vhd(14,8-14,17) (VHDL-1012) analyzing entity cont_disp INFO - C:/TFG/exp6_2/cont_disp.vhd(22,14-22,23) (VHDL-1010) analyzing architecture structure (VHDL-1481) Analyzing VHDL file C:/TFG/exp6_2/control_disp.vhd INFO - C:/TFG/exp6_2/control_disp.vhd(5,8-5,20) (VHDL-1012) analyzing entity control_disp INFO - C:/TFG/exp6_2/control_disp.vhd(14,14-14,26) (VHDL-1010) analyzing architecture control_arch (VHDL-1481) Analyzing VHDL file C:/TFG/exp6_2/div2.vhd INFO - C:/TFG/exp6_2/div2.vhd(14,8-14,12) (VHDL-1012) analyzing entity div2 INFO - C:/TFG/exp6_2/div2.vhd(22,14-22,23) (VHDL-1010) analyzing architecture structure (VHDL-1481) Analyzing VHDL file C:/TFG/exp6_2/dos_gpio/soc/dos_gpio_vhd.vhd INFO - C:/TFG/exp6_2/dos_gpio/soc/dos_gpio_vhd.vhd(4,8-4,20) (VHDL-1012) analyzing entity dos_gpio_vhd INFO - C:/TFG/exp6_2/dos_gpio/soc/dos_gpio_vhd.vhd(18,14-18,28) (VHDL-1010) analyzing architecture dos_gpio_vhd_a (VHDL-1481) Analyzing VHDL file C:/TFG/exp6_2/pll2.vhd INFO - C:/TFG/exp6_2/pll2.vhd(14,8-14,12) (VHDL-1012) analyzing entity pll2 INFO - C:/TFG/exp6_2/pll2.vhd(22,14-22,23) (VHDL-1010) analyzing architecture structure INFO - C:/TFG/exp6_2/proyecto_global/esquema_global.v(3,8-3,22) (VERI-1018) compiling module esquema_global INFO - C:/TFG/exp6_2/proyecto_global/esquema_global.v(3,1-145,10) (VERI-9000) elaborating module 'esquema_global' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(930,1-934,10) (VERI-9000) elaborating module 'OR2_uniq_1' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(278,1-285,10) (VERI-9000) elaborating module 'FD1S3AX_uniq_1' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(278,1-285,10) (VERI-9000) elaborating module 'FD1S3AX_uniq_2' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(278,1-285,10) (VERI-9000) elaborating module 'FD1S3AX_uniq_3' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(278,1-285,10) (VERI-9000) elaborating module 'FD1S3AX_uniq_4' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(278,1-285,10) (VERI-9000) elaborating module 'FD1S3AX_uniq_5' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(278,1-285,10) (VERI-9000) elaborating module 'FD1S3AX_uniq_6' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(278,1-285,10) (VERI-9000) elaborating module 'FD1S3AX_uniq_7' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(278,1-285,10) (VERI-9000) elaborating module 'FD1S3AX_uniq_8' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(278,1-285,10) (VERI-9000) elaborating module 'FD1S3AX_uniq_9' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(278,1-285,10) (VERI-9000) elaborating module 'FD1S3AX_uniq_10' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(278,1-285,10) (VERI-9000) elaborating module 'FD1S3AX_uniq_11' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(278,1-285,10) (VERI-9000) elaborating module 'FD1S3AX_uniq_12' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1124,1-1126,10) (VERI-9000) elaborating module 'VLO_uniq_1' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1124,1-1126,10) (VERI-9000) elaborating module 'VLO_uniq_2' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(43,1-47,10) (VERI-9000) elaborating module 'AND2_uniq_1' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_1' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_2' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_3' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_4' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_5' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_6' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_7' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_8' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(56,1-62,10) (VERI-9000) elaborating module 'AND4_uniq_1' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(56,1-62,10) (VERI-9000) elaborating module 'AND4_uniq_2' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(857,1-860,10) (VERI-9000) elaborating module 'OB_uniq_1' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(857,1-860,10) (VERI-9000) elaborating module 'OB_uniq_2' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(857,1-860,10) (VERI-9000) elaborating module 'OB_uniq_3' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(857,1-860,10) (VERI-9000) elaborating module 'OB_uniq_4' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(857,1-860,10) (VERI-9000) elaborating module 'OB_uniq_5' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(857,1-860,10) (VERI-9000) elaborating module 'OB_uniq_6' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(857,1-860,10) (VERI-9000) elaborating module 'OB_uniq_7' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(857,1-860,10) (VERI-9000) elaborating module 'OB_uniq_8' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(857,1-860,10) (VERI-9000) elaborating module 'OB_uniq_9' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(857,1-860,10) (VERI-9000) elaborating module 'OB_uniq_10' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(857,1-860,10) (VERI-9000) elaborating module 'OB_uniq_11' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(857,1-860,10) (VERI-9000) elaborating module 'OB_uniq_12' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(857,1-860,10) (VERI-9000) elaborating module 'OB_uniq_13' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(857,1-860,10) (VERI-9000) elaborating module 'OB_uniq_14' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(857,1-860,10) (VERI-9000) elaborating module 'OB_uniq_15' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(857,1-860,10) (VERI-9000) elaborating module 'OB_uniq_16' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(857,1-860,10) (VERI-9000) elaborating module 'OB_uniq_17' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(857,1-860,10) (VERI-9000) elaborating module 'OB_uniq_18' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(857,1-860,10) (VERI-9000) elaborating module 'OB_uniq_19' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(498,1-501,10) (VERI-9000) elaborating module 'IB_uniq_1' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(498,1-501,10) (VERI-9000) elaborating module 'IB_uniq_2' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(498,1-501,10) (VERI-9000) elaborating module 'IB_uniq_3' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(498,1-501,10) (VERI-9000) elaborating module 'IB_uniq_4' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(498,1-501,10) (VERI-9000) elaborating module 'IB_uniq_5' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1120,1-1122,10) (VERI-9000) elaborating module 'VHI_uniq_1' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1120,1-1122,10) (VERI-9000) elaborating module 'VHI_uniq_2' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1120,1-1122,10) (VERI-9000) elaborating module 'VHI_uniq_3' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1793,1-1798,10) (VERI-9000) elaborating module 'OSCH_uniq_1' INFO - C:/TFG/exp6_2/proyecto_global/esquema_global.v(75,1-75,68) (VERI-1231) going to vhdl side to elaborate module pll2 INFO - C:/TFG/exp6_2/pll2.vhd(14,8-14,12) (VHDL-1067) elaborating pll2_uniq_0(Structure) INFO - C:/TFG/exp6_2/pll2.vhd(109,5-110,33) (VHDL-1399) going to verilog side to elaborate module VLO INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1124,8-1124,11) (VERI-1018) compiling module VLO_uniq_3 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1124,1-1126,10) (VERI-9000) elaborating module 'VLO_uniq_3' INFO - C:/TFG/exp6_2/pll2.vhd(109,5-110,33) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/pll2.vhd(112,5-148,45) (VHDL-1399) going to verilog side to elaborate module EHXPLLJ INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1730,8-1730,15) (VERI-1018) compiling module EHXPLLJ_uniq_1 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1730,1-1786,10) (VERI-9000) elaborating module 'EHXPLLJ_uniq_1' INFO - C:/TFG/exp6_2/pll2.vhd(112,5-148,45) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/proyecto_global/esquema_global.v(75,1-75,68) (VERI-1232) back to verilog to continue elaboration INFO - C:/TFG/exp6_2/proyecto_global/esquema_global.v(76,1-76,59) (VERI-1231) going to vhdl side to elaborate module div2 INFO - C:/TFG/exp6_2/div2.vhd(14,8-14,12) (VHDL-1067) elaborating div2_uniq_0(Structure) INFO - C:/TFG/exp6_2/div2.vhd(60,5-62,27) (VHDL-1399) going to verilog side to elaborate module FD1P3DX INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,8-187,15) (VERI-1018) compiling module FD1P3DX_uniq_1 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_1' INFO - C:/TFG/exp6_2/div2.vhd(60,5-62,27) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/div2.vhd(64,5-65,33) (VHDL-1399) going to verilog side to elaborate module VHI INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1120,8-1120,11) (VERI-1018) compiling module VHI_uniq_4 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1120,1-1122,10) (VERI-9000) elaborating module 'VHI_uniq_4' INFO - C:/TFG/exp6_2/div2.vhd(64,5-65,33) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/div2.vhd(67,5-70,23) (VHDL-1399) going to verilog side to elaborate module FADD2B INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(138,8-138,14) (VERI-1018) compiling module FADD2B_uniq_1 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(138,1-142,10) (VERI-9000) elaborating module 'FADD2B_uniq_1' INFO - C:/TFG/exp6_2/div2.vhd(67,5-70,23) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/div2.vhd(72,5-74,40) (VHDL-1399) going to verilog side to elaborate module CU2 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(129,8-129,11) (VERI-1018) compiling module CU2_uniq_1 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(129,1-136,10) (VERI-9000) elaborating module 'CU2_uniq_1' INFO - C:/TFG/exp6_2/div2.vhd(72,5-74,40) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/div2.vhd(76,5-77,33) (VHDL-1399) going to verilog side to elaborate module VLO INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1124,8-1124,11) (VERI-1018) compiling module VLO_uniq_4 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1124,1-1126,10) (VERI-9000) elaborating module 'VLO_uniq_4' INFO - C:/TFG/exp6_2/div2.vhd(76,5-77,33) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/proyecto_global/esquema_global.v(76,1-76,59) (VERI-1232) back to verilog to continue elaboration INFO - C:/TFG/exp6_2/proyecto_global/esquema_global.v(77,1-82,67) (VERI-1231) going to vhdl side to elaborate module dos_gpio_vhd INFO - C:/TFG/exp6_2/dos_gpio/soc/dos_gpio_vhd.vhd(4,8-4,20) (VHDL-1067) elaborating dos_gpio_vhd_uniq_0(dos_gpio_vhd_a) INFO - C:/TFG/exp6_2/dos_gpio/soc/dos_gpio_vhd.vhd(36,1-47,6) (VHDL-1399) going to verilog side to elaborate module dos_gpio INFO - C:/TFG/exp6_2/dos_gpio/soc/dos_gpio.v(332,8-332,16) (VERI-1018) compiling module dos_gpio_uniq_1 INFO - C:/TFG/exp6_2/dos_gpio/soc/dos_gpio.v(332,1-895,10) (VERI-9000) elaborating module 'dos_gpio_uniq_1' INFO - C:/TFG/exp6_2/dos_gpio/soc/dos_gpio.v(48,1-325,10) (VERI-9000) elaborating module 'arbiter2_uniq_1' INFO - C:/TFG/exp6_2/dos_gpio/soc/../components/lm8/rtl/verilog/lm8_top.v(50,1-1126,10) (VERI-9000) elaborating module 'lm8_uniq_1' INFO - C:/TFG/exp6_2/dos_gpio/soc/../components/gpio/rtl/verilog/gpio.v(80,1-1887,10) (VERI-9000) elaborating module 'gpio_uniq_1' INFO - C:/TFG/exp6_2/dos_gpio/soc/../components/gpio/rtl/verilog/gpio.v(80,1-1887,10) (VERI-9000) elaborating module 'gpio_uniq_2' INFO - C:/TFG/exp6_2/dos_gpio/soc/../components/gpio/rtl/verilog/gpio.v(80,1-1887,10) (VERI-9000) elaborating module 'gpio_uniq_3' INFO - C:/TFG/exp6_2/dos_gpio/soc/../components/gpio/rtl/verilog/gpio.v(80,1-1887,10) (VERI-9000) elaborating module 'gpio_uniq_4' INFO - C:/TFG/exp6_2/dos_gpio/soc/../components/gpio/rtl/verilog/gpio.v(80,1-1887,10) (VERI-9000) elaborating module 'gpio_uniq_5' INFO - C:/TFG/exp6_2/dos_gpio/soc/../components/gpio/rtl/verilog/gpio.v(80,1-1887,10) (VERI-9000) elaborating module 'gpio_uniq_6' INFO - C:/TFG/exp6_2/dos_gpio/soc/../components/gpio/rtl/verilog/gpio.v(80,1-1887,10) (VERI-9000) elaborating module 'gpio_uniq_7' INFO - C:/TFG/exp6_2/dos_gpio/soc/../components/lm8/rtl/verilog/lm8_core.v(47,1-661,10) (VERI-9000) elaborating module 'lm8_core_uniq_1' INFO - C:/TFG/exp6_2/dos_gpio/soc/../components/lm8/rtl/verilog/lm8_idec.v(47,1-283,10) (VERI-9000) elaborating module 'lm8_idec_uniq_1' INFO - C:/TFG/exp6_2/dos_gpio/soc/../components/lm8/rtl/verilog/lm8_alu.v(47,1-137,10) (VERI-9000) elaborating module 'lm8_alu_uniq_1' INFO - C:/TFG/exp6_2/dos_gpio/soc/../components/lm8/rtl/verilog/lm8_flow_cntl.v(49,1-534,10) (VERI-9000) elaborating module 'lm8_flow_cntl_uniq_1' INFO - C:/TFG/exp6_2/dos_gpio/soc/../components/lm8/rtl/verilog/lm8_io_cntl.v(47,1-131,10) (VERI-9000) elaborating module 'lm8_io_cntl_uniq_1' INFO - C:/TFG/exp6_2/dos_gpio/soc/../components/lm8/rtl/verilog/lm8_interrupt.v(49,1-136,10) (VERI-9000) elaborating module 'lm8_interrupt_uniq_1' INFO - C:/TFG/exp6_2/dos_gpio/soc/dos_gpio.v(332,1-895,10) (VERI-9000) elaborating module 'dos_gpio_uniq_1' INFO - C:/TFG/exp6_2/dos_gpio/soc/dos_gpio.v(48,1-325,10) (VERI-9000) elaborating module 'arbiter2_uniq_1' INFO - C:/TFG/exp6_2/dos_gpio/soc/../components/lm8/rtl/verilog/lm8_top.v(50,1-1126,10) (VERI-9000) elaborating module 'lm8_uniq_1' INFO - C:/TFG/exp6_2/dos_gpio/soc/../components/gpio/rtl/verilog/gpio.v(80,1-1887,10) (VERI-9000) elaborating module 'gpio_uniq_1' INFO - C:/TFG/exp6_2/dos_gpio/soc/../components/gpio/rtl/verilog/gpio.v(80,1-1887,10) (VERI-9000) elaborating module 'gpio_uniq_2' INFO - C:/TFG/exp6_2/dos_gpio/soc/../components/gpio/rtl/verilog/gpio.v(80,1-1887,10) (VERI-9000) elaborating module 'gpio_uniq_3' INFO - C:/TFG/exp6_2/dos_gpio/soc/../components/gpio/rtl/verilog/gpio.v(80,1-1887,10) (VERI-9000) elaborating module 'gpio_uniq_4' INFO - C:/TFG/exp6_2/dos_gpio/soc/../components/gpio/rtl/verilog/gpio.v(80,1-1887,10) (VERI-9000) elaborating module 'gpio_uniq_5' INFO - C:/TFG/exp6_2/dos_gpio/soc/../components/gpio/rtl/verilog/gpio.v(80,1-1887,10) (VERI-9000) elaborating module 'gpio_uniq_6' INFO - C:/TFG/exp6_2/dos_gpio/soc/../components/gpio/rtl/verilog/gpio.v(80,1-1887,10) (VERI-9000) elaborating module 'gpio_uniq_7' INFO - C:/TFG/exp6_2/dos_gpio/soc/../components/lm8/rtl/verilog/lm8_core.v(47,1-661,10) (VERI-9000) elaborating module 'lm8_core_uniq_1' INFO - C:/TFG/exp6_2/dos_gpio/soc/../components/gpio/rtl/verilog/tpio.v(66,1-189,10) (VERI-9000) elaborating module 'tpio_uniq_1' INFO - C:/TFG/exp6_2/dos_gpio/soc/../components/gpio/rtl/verilog/tpio.v(66,1-189,10) (VERI-9000) elaborating module 'tpio_uniq_2' INFO - C:/TFG/exp6_2/dos_gpio/soc/../components/gpio/rtl/verilog/tpio.v(66,1-189,10) (VERI-9000) elaborating module 'tpio_uniq_3' INFO - C:/TFG/exp6_2/dos_gpio/soc/../components/gpio/rtl/verilog/tpio.v(66,1-189,10) (VERI-9000) elaborating module 'tpio_uniq_4' INFO - C:/TFG/exp6_2/dos_gpio/soc/../components/gpio/rtl/verilog/tpio.v(66,1-189,10) (VERI-9000) elaborating module 'tpio_uniq_5' INFO - C:/TFG/exp6_2/dos_gpio/soc/../components/gpio/rtl/verilog/tpio.v(66,1-189,10) (VERI-9000) elaborating module 'tpio_uniq_6' INFO - C:/TFG/exp6_2/dos_gpio/soc/../components/gpio/rtl/verilog/tpio.v(66,1-189,10) (VERI-9000) elaborating module 'tpio_uniq_7' INFO - C:/TFG/exp6_2/dos_gpio/soc/../components/gpio/rtl/verilog/tpio.v(66,1-189,10) (VERI-9000) elaborating module 'tpio_uniq_8' INFO - C:/TFG/exp6_2/dos_gpio/soc/../components/gpio/rtl/verilog/tpio.v(66,1-189,10) (VERI-9000) elaborating module 'tpio_uniq_9' INFO - C:/TFG/exp6_2/dos_gpio/soc/../components/gpio/rtl/verilog/tpio.v(66,1-189,10) (VERI-9000) elaborating module 'tpio_uniq_10' INFO - C:/TFG/exp6_2/dos_gpio/soc/../components/gpio/rtl/verilog/tpio.v(66,1-189,10) (VERI-9000) elaborating module 'tpio_uniq_11' INFO - C:/TFG/exp6_2/dos_gpio/soc/../components/gpio/rtl/verilog/tpio.v(66,1-189,10) (VERI-9000) elaborating module 'tpio_uniq_12' INFO - C:/TFG/exp6_2/dos_gpio/soc/../components/gpio/rtl/verilog/tpio.v(66,1-189,10) (VERI-9000) elaborating module 'tpio_uniq_13' INFO - C:/TFG/exp6_2/dos_gpio/soc/../components/gpio/rtl/verilog/tpio.v(66,1-189,10) (VERI-9000) elaborating module 'tpio_uniq_14' INFO - C:/TFG/exp6_2/dos_gpio/soc/../components/gpio/rtl/verilog/tpio.v(66,1-189,10) (VERI-9000) elaborating module 'tpio_uniq_15' INFO - C:/TFG/exp6_2/dos_gpio/soc/../components/gpio/rtl/verilog/tpio.v(66,1-189,10) (VERI-9000) elaborating module 'tpio_uniq_16' INFO - C:/TFG/exp6_2/dos_gpio/soc/../components/gpio/rtl/verilog/tpio.v(66,1-189,10) (VERI-9000) elaborating module 'tpio_uniq_17' INFO - C:/TFG/exp6_2/dos_gpio/soc/../components/gpio/rtl/verilog/tpio.v(66,1-189,10) (VERI-9000) elaborating module 'tpio_uniq_18' INFO - C:/TFG/exp6_2/dos_gpio/soc/../components/gpio/rtl/verilog/tpio.v(66,1-189,10) (VERI-9000) elaborating module 'tpio_uniq_19' INFO - C:/TFG/exp6_2/dos_gpio/soc/../components/gpio/rtl/verilog/tpio.v(66,1-189,10) (VERI-9000) elaborating module 'tpio_uniq_20' INFO - C:/TFG/exp6_2/dos_gpio/soc/../components/gpio/rtl/verilog/tpio.v(66,1-189,10) (VERI-9000) elaborating module 'tpio_uniq_21' INFO - C:/TFG/exp6_2/dos_gpio/soc/../components/gpio/rtl/verilog/tpio.v(66,1-189,10) (VERI-9000) elaborating module 'tpio_uniq_22' INFO - C:/TFG/exp6_2/dos_gpio/soc/../components/gpio/rtl/verilog/tpio.v(66,1-189,10) (VERI-9000) elaborating module 'tpio_uniq_23' INFO - C:/TFG/exp6_2/dos_gpio/soc/../components/gpio/rtl/verilog/tpio.v(66,1-189,10) (VERI-9000) elaborating module 'tpio_uniq_24' INFO - C:/TFG/exp6_2/dos_gpio/soc/../components/gpio/rtl/verilog/tpio.v(66,1-189,10) (VERI-9000) elaborating module 'tpio_uniq_25' INFO - C:/TFG/exp6_2/dos_gpio/soc/../components/gpio/rtl/verilog/tpio.v(66,1-189,10) (VERI-9000) elaborating module 'tpio_uniq_26' INFO - C:/TFG/exp6_2/dos_gpio/soc/../components/gpio/rtl/verilog/tpio.v(66,1-189,10) (VERI-9000) elaborating module 'tpio_uniq_27' INFO - C:/TFG/exp6_2/dos_gpio/soc/../components/gpio/rtl/verilog/tpio.v(66,1-189,10) (VERI-9000) elaborating module 'tpio_uniq_28' INFO - C:/TFG/exp6_2/dos_gpio/soc/../components/lm8/rtl/verilog/lm8_idec.v(47,1-283,10) (VERI-9000) elaborating module 'lm8_idec_uniq_1' INFO - C:/TFG/exp6_2/dos_gpio/soc/../components/lm8/rtl/verilog/lm8_alu.v(47,1-137,10) (VERI-9000) elaborating module 'lm8_alu_uniq_1' INFO - C:/TFG/exp6_2/dos_gpio/soc/../components/lm8/rtl/verilog/lm8_flow_cntl.v(49,1-534,10) (VERI-9000) elaborating module 'lm8_flow_cntl_uniq_1' INFO - C:/TFG/exp6_2/dos_gpio/soc/../components/lm8/rtl/verilog/lm8_io_cntl.v(47,1-131,10) (VERI-9000) elaborating module 'lm8_io_cntl_uniq_1' INFO - C:/TFG/exp6_2/dos_gpio/soc/../components/lm8/rtl/verilog/lm8_interrupt.v(49,1-136,10) (VERI-9000) elaborating module 'lm8_interrupt_uniq_1' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(82,1-87,10) (VERI-9000) elaborating module 'BB_uniq_1' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(82,1-87,10) (VERI-9000) elaborating module 'BB_uniq_2' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(82,1-87,10) (VERI-9000) elaborating module 'BB_uniq_3' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(82,1-87,10) (VERI-9000) elaborating module 'BB_uniq_4' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(82,1-87,10) (VERI-9000) elaborating module 'BB_uniq_5' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(82,1-87,10) (VERI-9000) elaborating module 'BB_uniq_6' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(82,1-87,10) (VERI-9000) elaborating module 'BB_uniq_7' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(82,1-87,10) (VERI-9000) elaborating module 'BB_uniq_8' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(82,1-87,10) (VERI-9000) elaborating module 'BB_uniq_9' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(82,1-87,10) (VERI-9000) elaborating module 'BB_uniq_10' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(82,1-87,10) (VERI-9000) elaborating module 'BB_uniq_11' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(82,1-87,10) (VERI-9000) elaborating module 'BB_uniq_12' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(82,1-87,10) (VERI-9000) elaborating module 'BB_uniq_13' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(82,1-87,10) (VERI-9000) elaborating module 'BB_uniq_14' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(82,1-87,10) (VERI-9000) elaborating module 'BB_uniq_15' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(82,1-87,10) (VERI-9000) elaborating module 'BB_uniq_16' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(82,1-87,10) (VERI-9000) elaborating module 'BB_uniq_17' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(82,1-87,10) (VERI-9000) elaborating module 'BB_uniq_18' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(82,1-87,10) (VERI-9000) elaborating module 'BB_uniq_19' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(82,1-87,10) (VERI-9000) elaborating module 'BB_uniq_20' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(82,1-87,10) (VERI-9000) elaborating module 'BB_uniq_21' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(82,1-87,10) (VERI-9000) elaborating module 'BB_uniq_22' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(82,1-87,10) (VERI-9000) elaborating module 'BB_uniq_23' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(82,1-87,10) (VERI-9000) elaborating module 'BB_uniq_24' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(82,1-87,10) (VERI-9000) elaborating module 'BB_uniq_25' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(82,1-87,10) (VERI-9000) elaborating module 'BB_uniq_26' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(82,1-87,10) (VERI-9000) elaborating module 'BB_uniq_27' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(82,1-87,10) (VERI-9000) elaborating module 'BB_uniq_28' INFO - C:/TFG/exp6_2/dos_gpio/soc/dos_gpio_vhd.vhd(36,1-47,6) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/proyecto_global/esquema_global.v(77,1-82,67) (VERI-1232) back to verilog to continue elaboration INFO - C:/TFG/exp6_2/proyecto_global/esquema_global.v(95,1-95,75) (VERI-1231) going to vhdl side to elaborate module control_disp INFO - C:/TFG/exp6_2/control_disp.vhd(5,8-5,20) (VHDL-1067) elaborating control_disp_uniq_0(control_arch) INFO - C:/TFG/exp6_2/proyecto_global/esquema_global.v(95,1-95,75) (VERI-1232) back to verilog to continue elaboration INFO - C:/TFG/exp6_2/proyecto_global/esquema_global.v(109,1-109,70) (VERI-1231) going to vhdl side to elaborate module cont_BCD INFO - C:/TFG/exp6_2/cont_BCD.vhd(14,8-14,16) (VHDL-1067) elaborating cont_BCD_uniq_0(Structure) INFO - C:/TFG/exp6_2/cont_BCD.vhd(89,5-90,51) (VHDL-1399) going to verilog side to elaborate module INV INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,8-563,11) (VERI-1018) compiling module INV_uniq_9 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_9' INFO - C:/TFG/exp6_2/cont_BCD.vhd(89,5-90,51) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/cont_BCD.vhd(92,5-93,51) (VHDL-1399) going to verilog side to elaborate module INV INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,8-563,11) (VERI-1018) compiling module INV_uniq_10 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_10' INFO - C:/TFG/exp6_2/cont_BCD.vhd(92,5-93,51) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/cont_BCD.vhd(95,5-98,44) (VHDL-1399) going to verilog side to elaborate module ROM16X1A INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1051,8-1051,16) (VERI-1018) compiling module ROM16X1A_uniq_1 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1051,1-1060,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_1' INFO - C:/TFG/exp6_2/cont_BCD.vhd(95,5-98,44) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/cont_BCD.vhd(100,5-102,27) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_1 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_1' INFO - C:/TFG/exp6_2/cont_BCD.vhd(100,5-102,27) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/cont_BCD.vhd(104,5-106,27) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_2 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_2' INFO - C:/TFG/exp6_2/cont_BCD.vhd(104,5-106,27) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/cont_BCD.vhd(108,5-110,27) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_3 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_3' INFO - C:/TFG/exp6_2/cont_BCD.vhd(108,5-110,27) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/cont_BCD.vhd(112,5-114,27) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_4 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_4' INFO - C:/TFG/exp6_2/cont_BCD.vhd(112,5-114,27) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/cont_BCD.vhd(116,5-118,27) (VHDL-1399) going to verilog side to elaborate module FD1P3DX INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,8-187,15) (VERI-1018) compiling module FD1P3DX_uniq_2 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_2' INFO - C:/TFG/exp6_2/cont_BCD.vhd(116,5-118,27) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/cont_BCD.vhd(120,5-122,27) (VHDL-1399) going to verilog side to elaborate module FD1P3DX INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,8-187,15) (VERI-1018) compiling module FD1P3DX_uniq_3 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_3' INFO - C:/TFG/exp6_2/cont_BCD.vhd(120,5-122,27) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/cont_BCD.vhd(124,5-126,27) (VHDL-1399) going to verilog side to elaborate module FD1P3DX INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,8-187,15) (VERI-1018) compiling module FD1P3DX_uniq_4 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_4' INFO - C:/TFG/exp6_2/cont_BCD.vhd(124,5-126,27) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/cont_BCD.vhd(128,5-130,27) (VHDL-1399) going to verilog side to elaborate module FD1P3DX INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,8-187,15) (VERI-1018) compiling module FD1P3DX_uniq_5 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_5' INFO - C:/TFG/exp6_2/cont_BCD.vhd(128,5-130,27) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/cont_BCD.vhd(132,5-133,33) (VHDL-1399) going to verilog side to elaborate module VLO INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1124,8-1124,11) (VERI-1018) compiling module VLO_uniq_5 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1124,1-1126,10) (VERI-9000) elaborating module 'VLO_uniq_5' INFO - C:/TFG/exp6_2/cont_BCD.vhd(132,5-133,33) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/cont_BCD.vhd(135,5-136,33) (VHDL-1399) going to verilog side to elaborate module VHI INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1120,8-1120,11) (VERI-1018) compiling module VHI_uniq_5 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1120,1-1122,10) (VERI-9000) elaborating module 'VHI_uniq_5' INFO - C:/TFG/exp6_2/cont_BCD.vhd(135,5-136,33) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/cont_BCD.vhd(138,5-141,23) (VHDL-1399) going to verilog side to elaborate module FADD2B INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(138,8-138,14) (VERI-1018) compiling module FADD2B_uniq_2 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(138,1-142,10) (VERI-9000) elaborating module 'FADD2B_uniq_2' INFO - C:/TFG/exp6_2/cont_BCD.vhd(138,5-141,23) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/cont_BCD.vhd(143,5-145,45) (VHDL-1399) going to verilog side to elaborate module CU2 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(129,8-129,11) (VERI-1018) compiling module CU2_uniq_2 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(129,1-136,10) (VERI-9000) elaborating module 'CU2_uniq_2' INFO - C:/TFG/exp6_2/cont_BCD.vhd(143,5-145,45) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/cont_BCD.vhd(147,5-149,45) (VHDL-1399) going to verilog side to elaborate module CU2 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(129,8-129,11) (VERI-1018) compiling module CU2_uniq_3 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(129,1-136,10) (VERI-9000) elaborating module 'CU2_uniq_3' INFO - C:/TFG/exp6_2/cont_BCD.vhd(147,5-149,45) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/proyecto_global/esquema_global.v(109,1-109,70) (VERI-1232) back to verilog to continue elaboration INFO - C:/TFG/exp6_2/proyecto_global/esquema_global.v(110,1-110,79) (VERI-1231) going to vhdl side to elaborate module cont_BCD INFO - C:/TFG/exp6_2/cont_BCD.vhd(14,8-14,16) (VHDL-1067) elaborating cont_BCD_uniq_1(Structure) INFO - C:/TFG/exp6_2/cont_BCD.vhd(89,5-90,51) (VHDL-1399) going to verilog side to elaborate module INV INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,8-563,11) (VERI-1018) compiling module INV_uniq_11 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_11' INFO - C:/TFG/exp6_2/cont_BCD.vhd(89,5-90,51) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/cont_BCD.vhd(92,5-93,51) (VHDL-1399) going to verilog side to elaborate module INV INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,8-563,11) (VERI-1018) compiling module INV_uniq_12 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_12' INFO - C:/TFG/exp6_2/cont_BCD.vhd(92,5-93,51) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/cont_BCD.vhd(95,5-98,44) (VHDL-1399) going to verilog side to elaborate module ROM16X1A INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1051,8-1051,16) (VERI-1018) compiling module ROM16X1A_uniq_2 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1051,1-1060,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_2' INFO - C:/TFG/exp6_2/cont_BCD.vhd(95,5-98,44) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/cont_BCD.vhd(100,5-102,27) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_5 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_5' INFO - C:/TFG/exp6_2/cont_BCD.vhd(100,5-102,27) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/cont_BCD.vhd(104,5-106,27) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_6 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_6' INFO - C:/TFG/exp6_2/cont_BCD.vhd(104,5-106,27) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/cont_BCD.vhd(108,5-110,27) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_7 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_7' INFO - C:/TFG/exp6_2/cont_BCD.vhd(108,5-110,27) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/cont_BCD.vhd(112,5-114,27) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_8 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_8' INFO - C:/TFG/exp6_2/cont_BCD.vhd(112,5-114,27) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/cont_BCD.vhd(116,5-118,27) (VHDL-1399) going to verilog side to elaborate module FD1P3DX INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,8-187,15) (VERI-1018) compiling module FD1P3DX_uniq_6 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_6' INFO - C:/TFG/exp6_2/cont_BCD.vhd(116,5-118,27) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/cont_BCD.vhd(120,5-122,27) (VHDL-1399) going to verilog side to elaborate module FD1P3DX INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,8-187,15) (VERI-1018) compiling module FD1P3DX_uniq_7 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_7' INFO - C:/TFG/exp6_2/cont_BCD.vhd(120,5-122,27) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/cont_BCD.vhd(124,5-126,27) (VHDL-1399) going to verilog side to elaborate module FD1P3DX INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,8-187,15) (VERI-1018) compiling module FD1P3DX_uniq_8 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_8' INFO - C:/TFG/exp6_2/cont_BCD.vhd(124,5-126,27) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/cont_BCD.vhd(128,5-130,27) (VHDL-1399) going to verilog side to elaborate module FD1P3DX INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,8-187,15) (VERI-1018) compiling module FD1P3DX_uniq_9 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_9' INFO - C:/TFG/exp6_2/cont_BCD.vhd(128,5-130,27) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/cont_BCD.vhd(132,5-133,33) (VHDL-1399) going to verilog side to elaborate module VLO INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1124,8-1124,11) (VERI-1018) compiling module VLO_uniq_6 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1124,1-1126,10) (VERI-9000) elaborating module 'VLO_uniq_6' INFO - C:/TFG/exp6_2/cont_BCD.vhd(132,5-133,33) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/cont_BCD.vhd(135,5-136,33) (VHDL-1399) going to verilog side to elaborate module VHI INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1120,8-1120,11) (VERI-1018) compiling module VHI_uniq_6 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1120,1-1122,10) (VERI-9000) elaborating module 'VHI_uniq_6' INFO - C:/TFG/exp6_2/cont_BCD.vhd(135,5-136,33) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/cont_BCD.vhd(138,5-141,23) (VHDL-1399) going to verilog side to elaborate module FADD2B INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(138,8-138,14) (VERI-1018) compiling module FADD2B_uniq_3 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(138,1-142,10) (VERI-9000) elaborating module 'FADD2B_uniq_3' INFO - C:/TFG/exp6_2/cont_BCD.vhd(138,5-141,23) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/cont_BCD.vhd(143,5-145,45) (VHDL-1399) going to verilog side to elaborate module CU2 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(129,8-129,11) (VERI-1018) compiling module CU2_uniq_4 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(129,1-136,10) (VERI-9000) elaborating module 'CU2_uniq_4' INFO - C:/TFG/exp6_2/cont_BCD.vhd(143,5-145,45) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/cont_BCD.vhd(147,5-149,45) (VHDL-1399) going to verilog side to elaborate module CU2 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(129,8-129,11) (VERI-1018) compiling module CU2_uniq_5 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(129,1-136,10) (VERI-9000) elaborating module 'CU2_uniq_5' INFO - C:/TFG/exp6_2/cont_BCD.vhd(147,5-149,45) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/proyecto_global/esquema_global.v(110,1-110,79) (VERI-1232) back to verilog to continue elaboration INFO - C:/TFG/exp6_2/proyecto_global/esquema_global.v(111,1-111,69) (VERI-1231) going to vhdl side to elaborate module cont_BCD INFO - C:/TFG/exp6_2/cont_BCD.vhd(14,8-14,16) (VHDL-1067) elaborating cont_BCD_uniq_2(Structure) INFO - C:/TFG/exp6_2/cont_BCD.vhd(89,5-90,51) (VHDL-1399) going to verilog side to elaborate module INV INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,8-563,11) (VERI-1018) compiling module INV_uniq_13 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_13' INFO - C:/TFG/exp6_2/cont_BCD.vhd(89,5-90,51) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/cont_BCD.vhd(92,5-93,51) (VHDL-1399) going to verilog side to elaborate module INV INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,8-563,11) (VERI-1018) compiling module INV_uniq_14 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_14' INFO - C:/TFG/exp6_2/cont_BCD.vhd(92,5-93,51) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/cont_BCD.vhd(95,5-98,44) (VHDL-1399) going to verilog side to elaborate module ROM16X1A INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1051,8-1051,16) (VERI-1018) compiling module ROM16X1A_uniq_3 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1051,1-1060,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_3' INFO - C:/TFG/exp6_2/cont_BCD.vhd(95,5-98,44) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/cont_BCD.vhd(100,5-102,27) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_9 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_9' INFO - C:/TFG/exp6_2/cont_BCD.vhd(100,5-102,27) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/cont_BCD.vhd(104,5-106,27) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_10 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_10' INFO - C:/TFG/exp6_2/cont_BCD.vhd(104,5-106,27) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/cont_BCD.vhd(108,5-110,27) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_11 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_11' INFO - C:/TFG/exp6_2/cont_BCD.vhd(108,5-110,27) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/cont_BCD.vhd(112,5-114,27) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_12 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_12' INFO - C:/TFG/exp6_2/cont_BCD.vhd(112,5-114,27) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/cont_BCD.vhd(116,5-118,27) (VHDL-1399) going to verilog side to elaborate module FD1P3DX INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,8-187,15) (VERI-1018) compiling module FD1P3DX_uniq_10 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_10' INFO - C:/TFG/exp6_2/cont_BCD.vhd(116,5-118,27) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/cont_BCD.vhd(120,5-122,27) (VHDL-1399) going to verilog side to elaborate module FD1P3DX INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,8-187,15) (VERI-1018) compiling module FD1P3DX_uniq_11 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_11' INFO - C:/TFG/exp6_2/cont_BCD.vhd(120,5-122,27) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/cont_BCD.vhd(124,5-126,27) (VHDL-1399) going to verilog side to elaborate module FD1P3DX INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,8-187,15) (VERI-1018) compiling module FD1P3DX_uniq_12 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_12' INFO - C:/TFG/exp6_2/cont_BCD.vhd(124,5-126,27) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/cont_BCD.vhd(128,5-130,27) (VHDL-1399) going to verilog side to elaborate module FD1P3DX INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,8-187,15) (VERI-1018) compiling module FD1P3DX_uniq_13 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_13' INFO - C:/TFG/exp6_2/cont_BCD.vhd(128,5-130,27) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/cont_BCD.vhd(132,5-133,33) (VHDL-1399) going to verilog side to elaborate module VLO INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1124,8-1124,11) (VERI-1018) compiling module VLO_uniq_7 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1124,1-1126,10) (VERI-9000) elaborating module 'VLO_uniq_7' INFO - C:/TFG/exp6_2/cont_BCD.vhd(132,5-133,33) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/cont_BCD.vhd(135,5-136,33) (VHDL-1399) going to verilog side to elaborate module VHI INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1120,8-1120,11) (VERI-1018) compiling module VHI_uniq_7 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1120,1-1122,10) (VERI-9000) elaborating module 'VHI_uniq_7' INFO - C:/TFG/exp6_2/cont_BCD.vhd(135,5-136,33) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/cont_BCD.vhd(138,5-141,23) (VHDL-1399) going to verilog side to elaborate module FADD2B INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(138,8-138,14) (VERI-1018) compiling module FADD2B_uniq_4 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(138,1-142,10) (VERI-9000) elaborating module 'FADD2B_uniq_4' INFO - C:/TFG/exp6_2/cont_BCD.vhd(138,5-141,23) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/cont_BCD.vhd(143,5-145,45) (VHDL-1399) going to verilog side to elaborate module CU2 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(129,8-129,11) (VERI-1018) compiling module CU2_uniq_6 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(129,1-136,10) (VERI-9000) elaborating module 'CU2_uniq_6' INFO - C:/TFG/exp6_2/cont_BCD.vhd(143,5-145,45) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/cont_BCD.vhd(147,5-149,45) (VHDL-1399) going to verilog side to elaborate module CU2 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(129,8-129,11) (VERI-1018) compiling module CU2_uniq_7 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(129,1-136,10) (VERI-9000) elaborating module 'CU2_uniq_7' INFO - C:/TFG/exp6_2/cont_BCD.vhd(147,5-149,45) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/proyecto_global/esquema_global.v(111,1-111,69) (VERI-1232) back to verilog to continue elaboration INFO - C:/TFG/exp6_2/proyecto_global/esquema_global.v(112,1-112,71) (VERI-1231) going to vhdl side to elaborate module divfrec1 INFO - C:/TFG/exp6_2/divfrec1.vhd(14,8-14,16) (VHDL-1067) elaborating divfrec1_uniq_0(Structure) INFO - C:/TFG/exp6_2/divfrec1.vhd(181,5-182,51) (VHDL-1399) going to verilog side to elaborate module INV INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,8-563,11) (VERI-1018) compiling module INV_uniq_15 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_15' INFO - C:/TFG/exp6_2/divfrec1.vhd(181,5-182,51) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/divfrec1.vhd(184,5-185,51) (VHDL-1399) going to verilog side to elaborate module INV INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,8-563,11) (VERI-1018) compiling module INV_uniq_16 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_16' INFO - C:/TFG/exp6_2/divfrec1.vhd(184,5-185,51) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/divfrec1.vhd(187,5-188,51) (VHDL-1399) going to verilog side to elaborate module INV INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,8-563,11) (VERI-1018) compiling module INV_uniq_17 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_17' INFO - C:/TFG/exp6_2/divfrec1.vhd(187,5-188,51) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/divfrec1.vhd(190,5-191,51) (VHDL-1399) going to verilog side to elaborate module INV INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,8-563,11) (VERI-1018) compiling module INV_uniq_18 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_18' INFO - C:/TFG/exp6_2/divfrec1.vhd(190,5-191,51) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/divfrec1.vhd(193,5-194,51) (VHDL-1399) going to verilog side to elaborate module INV INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,8-563,11) (VERI-1018) compiling module INV_uniq_19 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_19' INFO - C:/TFG/exp6_2/divfrec1.vhd(193,5-194,51) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/divfrec1.vhd(196,5-197,51) (VHDL-1399) going to verilog side to elaborate module INV INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,8-563,11) (VERI-1018) compiling module INV_uniq_20 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_20' INFO - C:/TFG/exp6_2/divfrec1.vhd(196,5-197,51) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/divfrec1.vhd(199,5-200,51) (VHDL-1399) going to verilog side to elaborate module INV INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,8-563,11) (VERI-1018) compiling module INV_uniq_21 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_21' INFO - C:/TFG/exp6_2/divfrec1.vhd(199,5-200,51) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/divfrec1.vhd(202,5-203,51) (VHDL-1399) going to verilog side to elaborate module INV INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,8-563,11) (VERI-1018) compiling module INV_uniq_22 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_22' INFO - C:/TFG/exp6_2/divfrec1.vhd(202,5-203,51) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/divfrec1.vhd(205,5-206,51) (VHDL-1399) going to verilog side to elaborate module INV INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,8-563,11) (VERI-1018) compiling module INV_uniq_23 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_23' INFO - C:/TFG/exp6_2/divfrec1.vhd(205,5-206,51) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/divfrec1.vhd(208,5-209,53) (VHDL-1399) going to verilog side to elaborate module INV INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,8-563,11) (VERI-1018) compiling module INV_uniq_24 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_24' INFO - C:/TFG/exp6_2/divfrec1.vhd(208,5-209,53) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/divfrec1.vhd(211,5-214,73) (VHDL-1399) going to verilog side to elaborate module ROM16X1A INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1051,8-1051,16) (VERI-1018) compiling module ROM16X1A_uniq_4 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1051,1-1060,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_4' INFO - C:/TFG/exp6_2/divfrec1.vhd(211,5-214,73) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/divfrec1.vhd(216,5-219,75) (VHDL-1399) going to verilog side to elaborate module ROM16X1A INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1051,8-1051,16) (VERI-1018) compiling module ROM16X1A_uniq_5 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1051,1-1060,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_5' INFO - C:/TFG/exp6_2/divfrec1.vhd(216,5-219,75) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/divfrec1.vhd(221,5-224,52) (VHDL-1399) going to verilog side to elaborate module ROM16X1A INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1051,8-1051,16) (VERI-1018) compiling module ROM16X1A_uniq_6 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1051,1-1060,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_6' INFO - C:/TFG/exp6_2/divfrec1.vhd(221,5-224,52) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/divfrec1.vhd(226,5-229,52) (VHDL-1399) going to verilog side to elaborate module ROM16X1A INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1051,8-1051,16) (VERI-1018) compiling module ROM16X1A_uniq_7 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1051,1-1060,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_7' INFO - C:/TFG/exp6_2/divfrec1.vhd(226,5-229,52) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/divfrec1.vhd(231,5-234,52) (VHDL-1399) going to verilog side to elaborate module ROM16X1A INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1051,8-1051,16) (VERI-1018) compiling module ROM16X1A_uniq_8 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1051,1-1060,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_8' INFO - C:/TFG/exp6_2/divfrec1.vhd(231,5-234,52) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/divfrec1.vhd(236,5-239,51) (VHDL-1399) going to verilog side to elaborate module ROM16X1A INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1051,8-1051,16) (VERI-1018) compiling module ROM16X1A_uniq_9 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1051,1-1060,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_9' INFO - C:/TFG/exp6_2/divfrec1.vhd(236,5-239,51) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/divfrec1.vhd(241,5-245,35) (VHDL-1399) going to verilog side to elaborate module ROM16X1A INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1051,8-1051,16) (VERI-1018) compiling module ROM16X1A_uniq_10 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1051,1-1060,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_10' INFO - C:/TFG/exp6_2/divfrec1.vhd(241,5-245,35) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/divfrec1.vhd(247,5-250,71) (VHDL-1399) going to verilog side to elaborate module ROM16X1A INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1051,8-1051,16) (VERI-1018) compiling module ROM16X1A_uniq_11 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1051,1-1060,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_11' INFO - C:/TFG/exp6_2/divfrec1.vhd(247,5-250,71) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/divfrec1.vhd(252,5-254,27) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_13 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_13' INFO - C:/TFG/exp6_2/divfrec1.vhd(252,5-254,27) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/divfrec1.vhd(256,5-258,27) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_14 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_14' INFO - C:/TFG/exp6_2/divfrec1.vhd(256,5-258,27) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/divfrec1.vhd(260,5-262,27) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_15 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_15' INFO - C:/TFG/exp6_2/divfrec1.vhd(260,5-262,27) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/divfrec1.vhd(264,5-266,27) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_16 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_16' INFO - C:/TFG/exp6_2/divfrec1.vhd(264,5-266,27) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/divfrec1.vhd(268,5-270,27) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_17 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_17' INFO - C:/TFG/exp6_2/divfrec1.vhd(268,5-270,27) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/divfrec1.vhd(272,5-274,27) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_18 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_18' INFO - C:/TFG/exp6_2/divfrec1.vhd(272,5-274,27) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/divfrec1.vhd(276,5-278,27) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_19 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_19' INFO - C:/TFG/exp6_2/divfrec1.vhd(276,5-278,27) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/divfrec1.vhd(280,5-282,27) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_20 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_20' INFO - C:/TFG/exp6_2/divfrec1.vhd(280,5-282,27) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/divfrec1.vhd(284,5-286,27) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_21 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_21' INFO - C:/TFG/exp6_2/divfrec1.vhd(284,5-286,27) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/divfrec1.vhd(288,5-290,27) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_22 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_22' INFO - C:/TFG/exp6_2/divfrec1.vhd(288,5-290,27) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/divfrec1.vhd(292,5-294,28) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_23 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_23' INFO - C:/TFG/exp6_2/divfrec1.vhd(292,5-294,28) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/divfrec1.vhd(296,5-298,28) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_24 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_24' INFO - C:/TFG/exp6_2/divfrec1.vhd(296,5-298,28) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/divfrec1.vhd(300,5-302,28) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_25 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_25' INFO - C:/TFG/exp6_2/divfrec1.vhd(300,5-302,28) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/divfrec1.vhd(304,5-306,28) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_26 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_26' INFO - C:/TFG/exp6_2/divfrec1.vhd(304,5-306,28) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/divfrec1.vhd(308,5-310,28) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_27 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_27' INFO - C:/TFG/exp6_2/divfrec1.vhd(308,5-310,28) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/divfrec1.vhd(312,5-314,28) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_28 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_28' INFO - C:/TFG/exp6_2/divfrec1.vhd(312,5-314,28) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/divfrec1.vhd(316,5-318,28) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_29 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_29' INFO - C:/TFG/exp6_2/divfrec1.vhd(316,5-318,28) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/divfrec1.vhd(320,5-322,28) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_30 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_30' INFO - C:/TFG/exp6_2/divfrec1.vhd(320,5-322,28) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/divfrec1.vhd(324,5-326,28) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_31 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_31' INFO - C:/TFG/exp6_2/divfrec1.vhd(324,5-326,28) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/divfrec1.vhd(328,5-330,28) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_32 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_32' INFO - C:/TFG/exp6_2/divfrec1.vhd(328,5-330,28) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/divfrec1.vhd(332,5-334,28) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_33 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_33' INFO - C:/TFG/exp6_2/divfrec1.vhd(332,5-334,28) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/divfrec1.vhd(336,5-338,27) (VHDL-1399) going to verilog side to elaborate module FD1P3DX INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,8-187,15) (VERI-1018) compiling module FD1P3DX_uniq_14 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_14' INFO - C:/TFG/exp6_2/divfrec1.vhd(336,5-338,27) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/divfrec1.vhd(340,5-342,27) (VHDL-1399) going to verilog side to elaborate module FD1P3DX INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,8-187,15) (VERI-1018) compiling module FD1P3DX_uniq_15 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_15' INFO - C:/TFG/exp6_2/divfrec1.vhd(340,5-342,27) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/divfrec1.vhd(344,5-346,27) (VHDL-1399) going to verilog side to elaborate module FD1P3DX INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,8-187,15) (VERI-1018) compiling module FD1P3DX_uniq_16 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_16' INFO - C:/TFG/exp6_2/divfrec1.vhd(344,5-346,27) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/divfrec1.vhd(348,5-350,27) (VHDL-1399) going to verilog side to elaborate module FD1P3DX INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,8-187,15) (VERI-1018) compiling module FD1P3DX_uniq_17 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_17' INFO - C:/TFG/exp6_2/divfrec1.vhd(348,5-350,27) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/divfrec1.vhd(352,5-354,27) (VHDL-1399) going to verilog side to elaborate module FD1P3DX INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,8-187,15) (VERI-1018) compiling module FD1P3DX_uniq_18 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_18' INFO - C:/TFG/exp6_2/divfrec1.vhd(352,5-354,27) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/divfrec1.vhd(356,5-358,27) (VHDL-1399) going to verilog side to elaborate module FD1P3DX INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,8-187,15) (VERI-1018) compiling module FD1P3DX_uniq_19 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_19' INFO - C:/TFG/exp6_2/divfrec1.vhd(356,5-358,27) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/divfrec1.vhd(360,5-362,27) (VHDL-1399) going to verilog side to elaborate module FD1P3DX INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,8-187,15) (VERI-1018) compiling module FD1P3DX_uniq_20 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_20' INFO - C:/TFG/exp6_2/divfrec1.vhd(360,5-362,27) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/divfrec1.vhd(364,5-366,27) (VHDL-1399) going to verilog side to elaborate module FD1P3DX INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,8-187,15) (VERI-1018) compiling module FD1P3DX_uniq_21 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_21' INFO - C:/TFG/exp6_2/divfrec1.vhd(364,5-366,27) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/divfrec1.vhd(368,5-370,27) (VHDL-1399) going to verilog side to elaborate module FD1P3DX INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,8-187,15) (VERI-1018) compiling module FD1P3DX_uniq_22 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_22' INFO - C:/TFG/exp6_2/divfrec1.vhd(368,5-370,27) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/divfrec1.vhd(372,5-374,27) (VHDL-1399) going to verilog side to elaborate module FD1P3DX INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,8-187,15) (VERI-1018) compiling module FD1P3DX_uniq_23 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_23' INFO - C:/TFG/exp6_2/divfrec1.vhd(372,5-374,27) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/divfrec1.vhd(376,5-378,28) (VHDL-1399) going to verilog side to elaborate module FD1P3DX INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,8-187,15) (VERI-1018) compiling module FD1P3DX_uniq_24 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_24' INFO - C:/TFG/exp6_2/divfrec1.vhd(376,5-378,28) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/divfrec1.vhd(380,5-382,28) (VHDL-1399) going to verilog side to elaborate module FD1P3DX INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,8-187,15) (VERI-1018) compiling module FD1P3DX_uniq_25 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_25' INFO - C:/TFG/exp6_2/divfrec1.vhd(380,5-382,28) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/divfrec1.vhd(384,5-386,28) (VHDL-1399) going to verilog side to elaborate module FD1P3DX INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,8-187,15) (VERI-1018) compiling module FD1P3DX_uniq_26 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_26' INFO - C:/TFG/exp6_2/divfrec1.vhd(384,5-386,28) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/divfrec1.vhd(388,5-390,28) (VHDL-1399) going to verilog side to elaborate module FD1P3DX INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,8-187,15) (VERI-1018) compiling module FD1P3DX_uniq_27 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_27' INFO - C:/TFG/exp6_2/divfrec1.vhd(388,5-390,28) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/divfrec1.vhd(392,5-394,28) (VHDL-1399) going to verilog side to elaborate module FD1P3DX INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,8-187,15) (VERI-1018) compiling module FD1P3DX_uniq_28 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_28' INFO - C:/TFG/exp6_2/divfrec1.vhd(392,5-394,28) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/divfrec1.vhd(396,5-398,28) (VHDL-1399) going to verilog side to elaborate module FD1P3DX INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,8-187,15) (VERI-1018) compiling module FD1P3DX_uniq_29 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_29' INFO - C:/TFG/exp6_2/divfrec1.vhd(396,5-398,28) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/divfrec1.vhd(400,5-402,28) (VHDL-1399) going to verilog side to elaborate module FD1P3DX INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,8-187,15) (VERI-1018) compiling module FD1P3DX_uniq_30 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_30' INFO - C:/TFG/exp6_2/divfrec1.vhd(400,5-402,28) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/divfrec1.vhd(404,5-406,28) (VHDL-1399) going to verilog side to elaborate module FD1P3DX INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,8-187,15) (VERI-1018) compiling module FD1P3DX_uniq_31 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_31' INFO - C:/TFG/exp6_2/divfrec1.vhd(404,5-406,28) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/divfrec1.vhd(408,5-410,28) (VHDL-1399) going to verilog side to elaborate module FD1P3DX INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,8-187,15) (VERI-1018) compiling module FD1P3DX_uniq_32 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_32' INFO - C:/TFG/exp6_2/divfrec1.vhd(408,5-410,28) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/divfrec1.vhd(412,5-414,28) (VHDL-1399) going to verilog side to elaborate module FD1P3DX INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,8-187,15) (VERI-1018) compiling module FD1P3DX_uniq_33 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_33' INFO - C:/TFG/exp6_2/divfrec1.vhd(412,5-414,28) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/divfrec1.vhd(416,5-418,28) (VHDL-1399) going to verilog side to elaborate module FD1P3DX INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,8-187,15) (VERI-1018) compiling module FD1P3DX_uniq_34 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_34' INFO - C:/TFG/exp6_2/divfrec1.vhd(416,5-418,28) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/divfrec1.vhd(420,5-421,33) (VHDL-1399) going to verilog side to elaborate module VHI INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1120,8-1120,11) (VERI-1018) compiling module VHI_uniq_8 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1120,1-1122,10) (VERI-9000) elaborating module 'VHI_uniq_8' INFO - C:/TFG/exp6_2/divfrec1.vhd(420,5-421,33) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/divfrec1.vhd(423,5-426,23) (VHDL-1399) going to verilog side to elaborate module FADD2B INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(138,8-138,14) (VERI-1018) compiling module FADD2B_uniq_5 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(138,1-142,10) (VERI-9000) elaborating module 'FADD2B_uniq_5' INFO - C:/TFG/exp6_2/divfrec1.vhd(423,5-426,23) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/divfrec1.vhd(428,5-430,45) (VHDL-1399) going to verilog side to elaborate module CU2 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(129,8-129,11) (VERI-1018) compiling module CU2_uniq_8 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(129,1-136,10) (VERI-9000) elaborating module 'CU2_uniq_8' INFO - C:/TFG/exp6_2/divfrec1.vhd(428,5-430,45) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/divfrec1.vhd(432,5-434,45) (VHDL-1399) going to verilog side to elaborate module CU2 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(129,8-129,11) (VERI-1018) compiling module CU2_uniq_9 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(129,1-136,10) (VERI-9000) elaborating module 'CU2_uniq_9' INFO - C:/TFG/exp6_2/divfrec1.vhd(432,5-434,45) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/divfrec1.vhd(436,5-438,45) (VHDL-1399) going to verilog side to elaborate module CU2 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(129,8-129,11) (VERI-1018) compiling module CU2_uniq_10 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(129,1-136,10) (VERI-9000) elaborating module 'CU2_uniq_10' INFO - C:/TFG/exp6_2/divfrec1.vhd(436,5-438,45) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/divfrec1.vhd(440,5-442,45) (VHDL-1399) going to verilog side to elaborate module CU2 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(129,8-129,11) (VERI-1018) compiling module CU2_uniq_11 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(129,1-136,10) (VERI-9000) elaborating module 'CU2_uniq_11' INFO - C:/TFG/exp6_2/divfrec1.vhd(440,5-442,45) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/divfrec1.vhd(444,5-446,45) (VHDL-1399) going to verilog side to elaborate module CU2 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(129,8-129,11) (VERI-1018) compiling module CU2_uniq_12 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(129,1-136,10) (VERI-9000) elaborating module 'CU2_uniq_12' INFO - C:/TFG/exp6_2/divfrec1.vhd(444,5-446,45) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/divfrec1.vhd(448,5-450,47) (VHDL-1399) going to verilog side to elaborate module CU2 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(129,8-129,11) (VERI-1018) compiling module CU2_uniq_13 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(129,1-136,10) (VERI-9000) elaborating module 'CU2_uniq_13' INFO - C:/TFG/exp6_2/divfrec1.vhd(448,5-450,47) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/divfrec1.vhd(452,5-454,47) (VHDL-1399) going to verilog side to elaborate module CU2 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(129,8-129,11) (VERI-1018) compiling module CU2_uniq_14 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(129,1-136,10) (VERI-9000) elaborating module 'CU2_uniq_14' INFO - C:/TFG/exp6_2/divfrec1.vhd(452,5-454,47) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/divfrec1.vhd(456,5-458,47) (VHDL-1399) going to verilog side to elaborate module CU2 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(129,8-129,11) (VERI-1018) compiling module CU2_uniq_15 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(129,1-136,10) (VERI-9000) elaborating module 'CU2_uniq_15' INFO - C:/TFG/exp6_2/divfrec1.vhd(456,5-458,47) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/divfrec1.vhd(460,5-462,47) (VHDL-1399) going to verilog side to elaborate module CU2 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(129,8-129,11) (VERI-1018) compiling module CU2_uniq_16 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(129,1-136,10) (VERI-9000) elaborating module 'CU2_uniq_16' INFO - C:/TFG/exp6_2/divfrec1.vhd(460,5-462,47) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/divfrec1.vhd(464,5-466,47) (VHDL-1399) going to verilog side to elaborate module CU2 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(129,8-129,11) (VERI-1018) compiling module CU2_uniq_17 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(129,1-136,10) (VERI-9000) elaborating module 'CU2_uniq_17' INFO - C:/TFG/exp6_2/divfrec1.vhd(464,5-466,47) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/divfrec1.vhd(468,5-470,41) (VHDL-1399) going to verilog side to elaborate module CU2 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(129,8-129,11) (VERI-1018) compiling module CU2_uniq_18 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(129,1-136,10) (VERI-9000) elaborating module 'CU2_uniq_18' INFO - C:/TFG/exp6_2/divfrec1.vhd(468,5-470,41) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/divfrec1.vhd(472,5-473,33) (VHDL-1399) going to verilog side to elaborate module VLO INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1124,8-1124,11) (VERI-1018) compiling module VLO_uniq_8 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1124,1-1126,10) (VERI-9000) elaborating module 'VLO_uniq_8' INFO - C:/TFG/exp6_2/divfrec1.vhd(472,5-473,33) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/proyecto_global/esquema_global.v(112,1-112,71) (VERI-1232) back to verilog to continue elaboration INFO - C:/TFG/exp6_2/proyecto_global/esquema_global.v(142,1-142,60) (VERI-1231) going to vhdl side to elaborate module DEC_DISP INFO - C:/TFG/exp6_2/DECODIF.vhd(4,8-4,16) (VHDL-1067) elaborating DEC_DISP_uniq_0(DEC_DISP_arch) INFO - C:/TFG/exp6_2/proyecto_global/esquema_global.v(142,1-142,60) (VERI-1232) back to verilog to continue elaboration INFO - C:/TFG/exp6_2/proyecto_global/esquema_global.v(143,1-143,57) (VERI-1231) going to vhdl side to elaborate module DEC_DISP INFO - C:/TFG/exp6_2/DECODIF.vhd(4,8-4,16) (VHDL-1067) elaborating DEC_DISP_uniq_1(DEC_DISP_arch) INFO - C:/TFG/exp6_2/proyecto_global/esquema_global.v(143,1-143,57) (VERI-1232) back to verilog to continue elaboration WARNING - C:/TFG/exp6_2/proyecto_global/esquema_global.v(141,1-141,38) (VERI-1927) port SEDSTDBY remains unconnected for this instance WARNING - C:/TFG/exp6_2/dos_gpio/soc/dos_gpio.v(605,1-638,35) (VERI-1927) port PIO_BOTH_IN remains unconnected for this instance WARNING - C:/TFG/exp6_2/dos_gpio/soc/dos_gpio.v(646,1-679,35) (VERI-1927) port PIO_BOTH_IN remains unconnected for this instance WARNING - C:/TFG/exp6_2/dos_gpio/soc/dos_gpio.v(687,1-720,35) (VERI-1927) port PIO_BOTH_IN remains unconnected for this instance WARNING - C:/TFG/exp6_2/dos_gpio/soc/dos_gpio.v(728,1-761,35) (VERI-1927) port PIO_IN remains unconnected for this instance WARNING - C:/TFG/exp6_2/dos_gpio/soc/dos_gpio.v(769,1-802,35) (VERI-1927) port PIO_IN remains unconnected for this instance WARNING - C:/TFG/exp6_2/dos_gpio/soc/dos_gpio.v(810,1-843,35) (VERI-1927) port PIO_BOTH_IN remains unconnected for this instance WARNING - C:/TFG/exp6_2/dos_gpio/soc/dos_gpio.v(851,1-884,35) (VERI-1927) port PIO_IN remains unconnected for this instance INFO - C:/TFG/exp6_2/cont_disp.vhd(14,8-14,17) (VHDL-1067) elaborating cont_disp(Structure) INFO - C:/TFG/exp6_2/cont_disp.vhd(102,5-103,51) (VHDL-1399) going to verilog side to elaborate module INV INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,8-563,11) (VERI-1018) compiling module INV_uniq_25 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_25' INFO - C:/TFG/exp6_2/cont_disp.vhd(102,5-103,51) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/cont_disp.vhd(105,5-106,51) (VHDL-1399) going to verilog side to elaborate module INV INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,8-563,11) (VERI-1018) compiling module INV_uniq_26 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_26' INFO - C:/TFG/exp6_2/cont_disp.vhd(105,5-106,51) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/cont_disp.vhd(108,5-109,51) (VHDL-1399) going to verilog side to elaborate module INV INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,8-563,11) (VERI-1018) compiling module INV_uniq_27 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_27' INFO - C:/TFG/exp6_2/cont_disp.vhd(108,5-109,51) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/cont_disp.vhd(111,5-112,51) (VHDL-1399) going to verilog side to elaborate module INV INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,8-563,11) (VERI-1018) compiling module INV_uniq_28 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_28' INFO - C:/TFG/exp6_2/cont_disp.vhd(111,5-112,51) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/cont_disp.vhd(114,5-115,51) (VHDL-1399) going to verilog side to elaborate module INV INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,8-563,11) (VERI-1018) compiling module INV_uniq_29 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_29' INFO - C:/TFG/exp6_2/cont_disp.vhd(114,5-115,51) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/cont_disp.vhd(117,5-120,73) (VHDL-1399) going to verilog side to elaborate module ROM16X1A INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1051,8-1051,16) (VERI-1018) compiling module ROM16X1A_uniq_12 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1051,1-1060,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_12' INFO - C:/TFG/exp6_2/cont_disp.vhd(117,5-120,73) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/cont_disp.vhd(122,5-125,45) (VHDL-1399) going to verilog side to elaborate module ROM16X1A INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1051,8-1051,16) (VERI-1018) compiling module ROM16X1A_uniq_13 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1051,1-1060,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_13' INFO - C:/TFG/exp6_2/cont_disp.vhd(122,5-125,45) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/cont_disp.vhd(127,5-129,27) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_34 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_34' INFO - C:/TFG/exp6_2/cont_disp.vhd(127,5-129,27) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/cont_disp.vhd(131,5-133,27) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_35 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_35' INFO - C:/TFG/exp6_2/cont_disp.vhd(131,5-133,27) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/cont_disp.vhd(135,5-137,27) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_36 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_36' INFO - C:/TFG/exp6_2/cont_disp.vhd(135,5-137,27) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/cont_disp.vhd(139,5-141,27) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_37 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_37' INFO - C:/TFG/exp6_2/cont_disp.vhd(139,5-141,27) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/cont_disp.vhd(143,5-145,27) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_38 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_38' INFO - C:/TFG/exp6_2/cont_disp.vhd(143,5-145,27) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/cont_disp.vhd(147,5-149,27) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_39 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_39' INFO - C:/TFG/exp6_2/cont_disp.vhd(147,5-149,27) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/cont_disp.vhd(151,5-153,27) (VHDL-1399) going to verilog side to elaborate module FD1P3DX INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,8-187,15) (VERI-1018) compiling module FD1P3DX_uniq_35 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_35' INFO - C:/TFG/exp6_2/cont_disp.vhd(151,5-153,27) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/cont_disp.vhd(155,5-157,27) (VHDL-1399) going to verilog side to elaborate module FD1P3DX INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,8-187,15) (VERI-1018) compiling module FD1P3DX_uniq_36 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_36' INFO - C:/TFG/exp6_2/cont_disp.vhd(155,5-157,27) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/cont_disp.vhd(159,5-161,27) (VHDL-1399) going to verilog side to elaborate module FD1P3DX INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,8-187,15) (VERI-1018) compiling module FD1P3DX_uniq_37 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_37' INFO - C:/TFG/exp6_2/cont_disp.vhd(159,5-161,27) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/cont_disp.vhd(163,5-165,27) (VHDL-1399) going to verilog side to elaborate module FD1P3DX INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,8-187,15) (VERI-1018) compiling module FD1P3DX_uniq_38 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_38' INFO - C:/TFG/exp6_2/cont_disp.vhd(163,5-165,27) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/cont_disp.vhd(167,5-169,27) (VHDL-1399) going to verilog side to elaborate module FD1P3DX INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,8-187,15) (VERI-1018) compiling module FD1P3DX_uniq_39 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_39' INFO - C:/TFG/exp6_2/cont_disp.vhd(167,5-169,27) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/cont_disp.vhd(171,5-173,27) (VHDL-1399) going to verilog side to elaborate module FD1P3DX INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,8-187,15) (VERI-1018) compiling module FD1P3DX_uniq_40 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_40' INFO - C:/TFG/exp6_2/cont_disp.vhd(171,5-173,27) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/cont_disp.vhd(175,5-176,33) (VHDL-1399) going to verilog side to elaborate module VLO INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1124,8-1124,11) (VERI-1018) compiling module VLO_uniq_9 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1124,1-1126,10) (VERI-9000) elaborating module 'VLO_uniq_9' INFO - C:/TFG/exp6_2/cont_disp.vhd(175,5-176,33) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/cont_disp.vhd(178,5-179,33) (VHDL-1399) going to verilog side to elaborate module VHI INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1120,8-1120,11) (VERI-1018) compiling module VHI_uniq_9 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1120,1-1122,10) (VERI-9000) elaborating module 'VHI_uniq_9' INFO - C:/TFG/exp6_2/cont_disp.vhd(178,5-179,33) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/cont_disp.vhd(181,5-184,23) (VHDL-1399) going to verilog side to elaborate module FADD2B INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(138,8-138,14) (VERI-1018) compiling module FADD2B_uniq_6 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(138,1-142,10) (VERI-9000) elaborating module 'FADD2B_uniq_6' INFO - C:/TFG/exp6_2/cont_disp.vhd(181,5-184,23) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/cont_disp.vhd(186,5-188,45) (VHDL-1399) going to verilog side to elaborate module CU2 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(129,8-129,11) (VERI-1018) compiling module CU2_uniq_19 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(129,1-136,10) (VERI-9000) elaborating module 'CU2_uniq_19' INFO - C:/TFG/exp6_2/cont_disp.vhd(186,5-188,45) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/cont_disp.vhd(190,5-192,45) (VHDL-1399) going to verilog side to elaborate module CU2 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(129,8-129,11) (VERI-1018) compiling module CU2_uniq_20 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(129,1-136,10) (VERI-9000) elaborating module 'CU2_uniq_20' INFO - C:/TFG/exp6_2/cont_disp.vhd(190,5-192,45) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6_2/cont_disp.vhd(194,5-196,45) (VHDL-1399) going to verilog side to elaborate module CU2 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(129,8-129,11) (VERI-1018) compiling module CU2_uniq_21 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(129,1-136,10) (VERI-9000) elaborating module 'CU2_uniq_21' INFO - C:/TFG/exp6_2/cont_disp.vhd(194,5-196,45) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_25' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_26' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_27' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_28' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_29' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1051,1-1060,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_12' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1051,1-1060,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_13' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_34' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_35' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_36' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_37' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_38' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_39' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_35' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_36' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_37' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_38' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_39' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_40' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1124,1-1126,10) (VERI-9000) elaborating module 'VLO_uniq_9' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1120,1-1122,10) (VERI-9000) elaborating module 'VHI_uniq_9' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(138,1-142,10) (VERI-9000) elaborating module 'FADD2B_uniq_6' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(129,1-136,10) (VERI-9000) elaborating module 'CU2_uniq_19' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(129,1-136,10) (VERI-9000) elaborating module 'CU2_uniq_20' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(129,1-136,10) (VERI-9000) elaborating module 'CU2_uniq_21' Done: design load finished with (0) errors, and (15) warnings