Project Settings |
---|
Project Name | proj_1 | Implementation Name | proyecto_global |
Top Module | esquema_global | Pipelining | 1 |
Retiming | 0 | Resource Sharing | 1 |
Fanout Guide | 1000 | Disable I/O Insertion | 0 |
Disable Sequential Optimizations | 0 | Clock Conversion | 1 |
Run Status |
Job Name |
Status |
|
|
|
CPU Time |
Real Time |
Memory |
Date/Time |
(compiler) | Complete |
22 |
76 |
0 |
- |
0m:02s |
- |
17/09/2017 19:57:43 |
(premap) | Complete |
2 |
1 |
0 |
0m:00s |
0m:00s |
141MB |
17/09/2017 19:57:45 |
(fpga_mapper) | Complete |
14 |
6 |
0 |
0m:01s |
0m:01s |
144MB |
17/09/2017 19:57:47 |
Multi-srs Generator |
Complete | | | | | | | 17/09/2017 19:57:44 |
Area Summary |
|
Register bits | 33 |
I/O cells | 22 |
Block RAMs
(v_ram) | 0 |
DSPs
(dsp_used) | 0 |
ORCA LUTs
(total_luts) | 14 |
| |
Timing Summary |
|
Clock Name | Req Freq | Est Freq | Slack |
divfrec1|tdataout20_derived_clock | 2.1 MHz | 334.2 MHz | 477.777 |
esquema_global|N_25_inferred_clock | 2.1 MHz | 201.0 MHz | 475.795 |
System | 1.0 MHz | 1.9 MHz | 480.298 |
Optimizations Summary |
Combined Clock Conversion | 1 / 1 |
| |
|