Project Settings
Project Name proj_1 Implementation Name proyecto_global
Top Module esquema_global Pipelining 1
Retiming 0 Resource Sharing 1
Fanout Guide 1000 Disable I/O Insertion 0
Disable Sequential Optimizations 0 Clock Conversion 1

Run Status
Job Name Status CPU Time Real Time Memory Date/Time
(compiler)Complete 75 361 0 - 0m:02s - 27/09/2017
6:09:17
(premap)Complete 2 5 0 0m:00s 0m:00s 146MB 27/09/2017
6:09:19
(fpga_mapper)Complete 101 27 0 0m:03s 0m:03s 175MB 27/09/2017
6:09:23
Multi-srs Generator Complete27/09/2017
6:09:18

Area Summary
Register bits 197 I/O cells 28
Block RAMs (v_ram) 0 DSPs (dsp_used) 0
ORCA LUTs (total_luts) 320

Timing Summary
Clock NameReq FreqEst FreqSlack
div2|tdataout0_derived_clock1.0 MHz133.2 MHz1984.991
esquema_global|N_48_inferred_clock2.1 MHz201.0 MHz475.795
esquema_global|clk_ext_sal1.0 MHzNANA
esquema_global|clk_reg_inferred_clock1.0 MHzNANA
pll2|CLKOS2_inferred_clock1.0 MHz165.2 MHz993.946
pll2|CLKOS3_inferred_clock1.0 MHz343.8 MHz997.091
System1.0 MHz73.8 MHz986.453

Optimizations Summary
Combined Clock Conversion 2 / 4