PAR: Place And Route Diamond Version 3.8.0.115.3. Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2016 Lattice Semiconductor Corporation, All rights reserved. Wed Sep 20 02:07:36 2017 C:/lscc/diamond/3.8/ispfpga\bin\nt\par -f proy_glob_proy_glob.p2t proy_glob_proy_glob_map.ncd proy_glob_proy_glob.dir proy_glob_proy_glob.prf -gui -msgset C:/TFG/exp7/promote.xml Preference file: proy_glob_proy_glob.prf. Cost Table Summary Level/ Number Worst Timing Worst Timing Run NCD Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status ---------- -------- ----- ------ ----------- ----------- ---- ------ 5_1 * 0 - - - - 29 Complete * : Design saved. Total (real) run time for 1-seed: 29 secs par done! Lattice Place and Route Report for Design "proy_glob_proy_glob_map.ncd" Wed Sep 20 02:07:36 2017 Best Par Run PAR: Place And Route Diamond Version 3.8.0.115.3. Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset C:/TFG/exp7/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF proy_glob_proy_glob_map.ncd proy_glob_proy_glob.dir/5_1.ncd proy_glob_proy_glob.prf Preference file: proy_glob_proy_glob.prf. Placement level-cost: 5-1. Routing Iterations: 6 Loading design for application par from file proy_glob_proy_glob_map.ncd. Design name: proy_glob NCD version: 3.3 Vendor: LATTICE Device: LCMXO2-7000HE Package: TQFP144 Performance: 4 Loading device for application par from file 'xo2c7000.nph' in environment: C:/lscc/diamond/3.8/ispfpga. Package Status: Final Version 1.39. Performance Hardware Data Status: Final Version 34.4. License checked out. Ignore Preference Error(s): True Device utilization summary: PIO (prelim) 44+4(JTAG)/336 14% used 44+4(JTAG)/115 42% bonded IOLOGIC 8/336 2% used SLICE 1426/3432 41% used GSR 1/1 100% used JTAG 1/1 100% used EBR 16/26 61% used INFO: Design contains pre-loadable EBR during configuration that has a requirement: Since the GSR is disabled for the EBR, make sure write enable and chip enable are inactive during wake-up, so that the pre-loaded initialization values will not be corrupted during wake-up state. Number of Signals: 4487 Number of Connections: 13734 Pin Constraint Summary: 12 out of 44 pins locked (27% locked). The following 2 signals are selected to use the primary clock routing resources: N_2 (driver: I27/SLICE_0, clk load #: 904) jtaghub16_jtck (driver: xo2chub/genblk7.jtagf_u, clk load #: 41) The following 8 signals are selected to use the secondary clock routing resources: I1/lm32_inst/LM32/cpu/stall_m_i_0_a2 (driver: I1/lm32_inst/LM32/cpu/SLICE_1215, clk load #: 0, sr load #: 0, ce load #: 257) I1/lm32_inst/LM32/cpu/stall_d_i (driver: I1/lm32_inst/LM32/cpu/decoder/SLICE_1459, clk load #: 0, sr load #: 0, ce load #: 64) jtaghub16_jrstn (driver: xo2chub/genblk7.jtagf_u, clk load #: 0, sr load #: 40, ce load #: 0) I1/lm32_inst/flash/core_inst/main_sm_ns_0_o2_0_RNI75UB[1] (driver: I1/lm32_inst/flash/core_inst/SLICE_1230, clk load #: 0, sr load #: 0, ce load #: 17) I1/lm32_inst/LM32/cpu/load_store_unit/d_cti_o_0_sqmuxa (driver: I1/lm32_inst/LM32/cpu/SLICE_1378, clk load #: 0, sr load #: 0, ce load #: 17) I1/lm32_inst/counter[2] (driver: I1/lm32_inst/SLICE_967, clk load #: 0, sr load #: 16, ce load #: 0) I1/lm32_inst/sram/core_inst/N_143_i (driver: I1/lm32_inst/sram/core_inst/SLICE_1249, clk load #: 0, sr load #: 0, ce load #: 16) I1/lm32_inst/LM32/debug_rom/write_data_0_sqmuxa (driver: I1/lm32_inst/SLICE_967, clk load #: 0, sr load #: 0, ce load #: 16) Signal I1/lm32_inst/counter[2] is selected as Global Set/Reset. . Starting Placer Phase 0. .............. Finished Placer Phase 0. REAL time: 5 secs Starting Placer Phase 1. ...................... Placer score = 1327237. Finished Placer Phase 1. REAL time: 10 secs Starting Placer Phase 2. . Placer score = 1316629 Finished Placer Phase 2. REAL time: 11 secs Clock Report Global Clock Resources: CLK_PIN : 0 out of 8 (0%) PLL : 0 out of 2 (0%) DCM : 0 out of 2 (0%) DCC : 0 out of 8 (0%) Quadrants All (TL, TR, BL, BR) - Global Clocks: PRIMARY "N_2" from Q0 on comp "I27/SLICE_0" on site "R2C19B", clk load = 904 PRIMARY "jtaghub16_jtck" from JTCK on comp "xo2chub/genblk7.jtagf_u" on site "JTAG", clk load = 41 SECONDARY "I1/lm32_inst/LM32/cpu/stall_m_i_0_a2" from F1 on comp "I1/lm32_inst/LM32/cpu/SLICE_1215" on site "R21C18B", clk load = 0, ce load = 257, sr load = 0 SECONDARY "I1/lm32_inst/LM32/cpu/stall_d_i" from F0 on comp "I1/lm32_inst/LM32/cpu/decoder/SLICE_1459" on site "R21C20B", clk load = 0, ce load = 64, sr load = 0 SECONDARY "jtaghub16_jrstn" from JRSTN on comp "xo2chub/genblk7.jtagf_u" on site "JTAG", clk load = 0, ce load = 0, sr load = 40 SECONDARY "I1/lm32_inst/flash/core_inst/main_sm_ns_0_o2_0_RNI75UB[1]" from F0 on comp "I1/lm32_inst/flash/core_inst/SLICE_1230" on site "R21C20C", clk load = 0, ce load = 17, sr load = 0 SECONDARY "I1/lm32_inst/LM32/cpu/load_store_unit/d_cti_o_0_sqmuxa" from F0 on comp "I1/lm32_inst/LM32/cpu/SLICE_1378" on site "R14C20D", clk load = 0, ce load = 17, sr load = 0 SECONDARY "I1/lm32_inst/counter[2]" from Q0 on comp "I1/lm32_inst/SLICE_967" on site "R14C20B", clk load = 0, ce load = 0, sr load = 16 SECONDARY "I1/lm32_inst/sram/core_inst/N_143_i" from F1 on comp "I1/lm32_inst/sram/core_inst/SLICE_1249" on site "R21C20D", clk load = 0, ce load = 16, sr load = 0 SECONDARY "I1/lm32_inst/LM32/debug_rom/write_data_0_sqmuxa" from F1 on comp "I1/lm32_inst/SLICE_967" on site "R14C20B", clk load = 0, ce load = 16, sr load = 0 PRIMARY : 2 out of 8 (25%) SECONDARY: 8 out of 8 (100%) Edge Clocks: No edge clock selected. I/O Usage Summary (final): 44 + 4(JTAG) out of 336 (14.3%) PIO sites used. 44 + 4(JTAG) out of 115 (41.7%) bonded PIO sites used. Number of PIO comps: 44; differential: 0. Number of Vref pins used: 0. I/O Bank Usage Summary: +----------+----------------+------------+-----------+ | I/O Bank | Usage | Bank Vccio | Bank Vref | +----------+----------------+------------+-----------+ | 0 | 9 / 28 ( 32%) | 2.5V | - | | 1 | 9 / 29 ( 31%) | 3.3V | - | | 2 | 23 / 29 ( 79%) | 2.5V | - | | 3 | 2 / 9 ( 22%) | 3.3V | - | | 4 | 0 / 10 ( 0%) | - | - | | 5 | 1 / 10 ( 10%) | 3.3V | - | +----------+----------------+------------+-----------+ Total placer CPU time: 10 secs Dumping design to file proy_glob_proy_glob.dir/5_1.ncd. ----------------------------------------------------------------- INFO - par: ASE feature is off due to non timing-driven settings. ----------------------------------------------------------------- 0 connections routed; 13734 unrouted. Starting router resource preassignment WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew. Signal=sal_osc_c loads=1 clock_loads=1 Signal=I1/lm32_inst/LM32/jtag_update loads=1 clock_loads=1 Completed router resource preassignment. Real time: 14 secs Start NBR router at 02:07:50 09/20/17 ***************************************************************** Info: NBR allows conflicts(one node used by more than one signal) in the earlier iterations. In each iteration, it tries to solve the conflicts while keeping the critical connections routed as short as possible. The routing process is said to be completed when no conflicts exist and all connections are routed. Note: NBR uses a different method to calculate timing slacks. The worst slack and total negative slack may not be the same as that in TRCE report. You should always run TRCE to verify your design. ***************************************************************** Start NBR special constraint process at 02:07:51 09/20/17 Start NBR section for initial routing at 02:07:51 09/20/17 Level 4, iteration 1 857(0.23%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; real time: 18 secs Info: Initial congestion level at 75% usage is 5 Info: Initial congestion area at 75% usage is 136 (13.60%) Start NBR section for normal routing at 02:07:54 09/20/17 Level 4, iteration 1 383(0.10%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; real time: 21 secs Level 4, iteration 2 189(0.05%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; real time: 22 secs Level 4, iteration 3 123(0.03%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; real time: 22 secs Level 4, iteration 4 63(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; real time: 23 secs Level 4, iteration 5 47(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; real time: 23 secs Level 4, iteration 6 33(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; real time: 24 secs Level 4, iteration 7 28(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; real time: 24 secs Level 4, iteration 8 13(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; real time: 24 secs Level 4, iteration 9 7(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; real time: 24 secs Level 4, iteration 10 9(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; real time: 25 secs Level 4, iteration 11 8(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; real time: 25 secs Level 4, iteration 12 4(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; real time: 25 secs Level 4, iteration 13 2(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; real time: 25 secs Level 4, iteration 14 1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; real time: 25 secs Level 4, iteration 15 0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; real time: 25 secs Start NBR section for re-routing at 02:08:01 09/20/17 Level 4, iteration 1 0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; real time: 25 secs Start NBR section for post-routing at 02:08:01 09/20/17 End NBR router with 0 unrouted connection NBR Summary ----------- Number of unrouted connections : 0 (0.00%) Number of connections with timing violations : 0 (0.00%) Estimated worst slack<setup> : <n/a> Timing score<setup> : 0 ----------- Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored. WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew. Signal=sal_osc_c loads=1 clock_loads=1 Signal=I1/lm32_inst/LM32/jtag_update loads=1 clock_loads=1 Total CPU time 25 secs Total REAL time: 26 secs Completely routed. End of route. 13734 routed (100.00%); 0 unrouted. Hold time timing score: 0, hold timing errors: 0 Timing score: 0 Dumping design to file proy_glob_proy_glob.dir/5_1.ncd. All signals are completely routed. PAR_SUMMARY::Run status = completed PAR_SUMMARY::Number of unrouted conns = 0 PAR_SUMMARY::Worst slack<setup/<ns>> = <n/a> PAR_SUMMARY::Timing score<setup/<ns>> = <n/a> PAR_SUMMARY::Worst slack<hold /<ns>> = <n/a> PAR_SUMMARY::Timing score<hold /<ns>> = <n/a> PAR_SUMMARY::Number of errors = 0 Total CPU time to completion: 28 secs Total REAL time to completion: 29 secs par done! Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2016 Lattice Semiconductor Corporation, All rights reserved.