Project Settings |
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Project Name | proj_1 | Implementation Name | proy_glob |
Top Module | proy_glob | Pipelining | 1 |
Retiming | 0 | Resource Sharing | 1 |
Fanout Guide | 1000 | Disable I/O Insertion | 0 |
Disable Sequential Optimizations | 0 | Clock Conversion | 1 |
Run Status |
Job Name |
Status |
|
|
|
CPU Time |
Real Time |
Memory |
Date/Time |
(compiler) | Complete |
143 |
273 |
0 |
- |
0m:06s |
- |
20/09/2017 2:06:52 |
(premap) | Complete |
5 |
5 |
0 |
0m:01s |
0m:01s |
151MB |
20/09/2017 2:06:56 |
(fpga_mapper) | Complete |
148 |
16 |
0 |
0m:21s |
0m:22s |
242MB |
20/09/2017 2:07:18 |
Multi-srs Generator |
Complete | | | | 0m:01s | | | 20/09/2017 2:06:54 |
Area Summary |
|
Register bits | 1449 |
I/O cells | 44 |
Block RAMs
(v_ram) | 12 |
DSPs
(dsp_used) | 0 |
ORCA LUTs
(total_luts) | 2397 |
| |
Timing Summary |
|
Clock Name | Req Freq | Est Freq | Slack |
div2|tdataout0_derived_clock | 1.0 MHz | 123.8 MHz | 1983.840 |
jtag_cores|jtck | 1.0 MHz | 636.2 MHz | 998.428 |
jtag_lm32|REG_UPDATE_inferred_clock | 1.0 MHz | 582.3 MHz | 998.283 |
proy_glob|sal_osc | 1.0 MHz | NA | NA |
System | 1.0 MHz | 459.2 MHz | 997.822 |
Optimizations Summary |
Combined Clock Conversion | 2 / 2 |
| |
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