Synthesis Report #Build: Synplify Pro L-2016.03L-1, Build 097R, Jul 4 2016 #install: C:\lscc\diamond\3.8\synpbase #OS: Windows 8 6.2 #Hostname: RORDRIGO # Wed Sep 20 02:06:46 2017 #Implementation: proy_glob Synopsys HDL Compiler, version comp2016q2rc, Build 192R, built Jul 5 2016 @N|Running in 64-bit mode Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Synopsys VHDL Compiler, version comp2016q2rc, Build 192R, built Jul 5 2016 @N|Running in 64-bit mode Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. @N: CD720 :"C:\lscc\diamond\3.8\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns @N:"C:\TFG\exp7\div2.vhd":14:7:14:10|Top entity is set to div2. VHDL syntax check successful! File C:\TFG\exp7\mic32\soc\mic32_vhd.vhd changed - recompiling At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB) Process completed successfully. # Wed Sep 20 02:06:46 2017 ###########################################################] Synopsys Verilog Compiler, version comp2016q2rc, Build 192R, built Jul 5 2016 @N|Running in 64-bit mode Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. @I::"C:\lscc\diamond\3.8\synpbase\lib\lucent\machxo2.v" (library work) @I::"C:\lscc\diamond\3.8\synpbase\lib\lucent\pmi_def.v" (library work) @I::"C:\lscc\diamond\3.8\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__) @I::"C:\lscc\diamond\3.8\synpbase\lib\vlog\umr_capim.v" (library snps_haps) @I::"C:\lscc\diamond\3.8\synpbase\lib\vlog\scemi_objects.v" (library snps_haps) @I::"C:\lscc\diamond\3.8\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps) @I::"C:\TFG\exp7\proy_glob\proy_glob.v" (library work) @I::"C:\TFG\exp7\mic32\soc\mic32.v" (library work) @I:"C:\TFG\exp7\mic32\soc\mic32.v":"C:\TFG\exp7\mic32\soc\system_conf.v" (library work) @I:"C:\TFG\exp7\mic32\soc\mic32.v":"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v" (library work) @I:"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\TFG\exp7\mic32\soc\pmi_def.v" (library work) @I:"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\typeb.v" (library work) @I:"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\typea.v" (library work) @I:"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\jtag_cores.v" (library work) @I:"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\jtag_cores.v":"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_include.v" (library work) @I:"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\jtag_lm32.v" (library work) @I:"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_jtag.v" (library work) @I:"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_addsub.v" (library work) @I:"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_adder.v" (library work) @I:"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v" (library work) @W: CS141 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v":652:9:652:17|Unrecognized synthesis directive attribute. Verify the correct directive name. @W: CS141 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v":653:9:653:17|Unrecognized synthesis directive attribute. Verify the correct directive name. @I:"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v":"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_functions.v" (library work) @N: CG334 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v":2773:13:2773:25|Read directive translate_off. @N: CG333 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v":2786:13:2786:24|Read directive translate_on. @I:"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_dcache.v" (library work) @I:"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_debug.v" (library work) @I:"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_decoder.v" (library work) @I:"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_icache.v" (library work) @I:"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_instruction_unit.v" (library work) @I:"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_interrupt.v" (library work) @W: CS141 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_interrupt.v":130:9:130:17|Unrecognized synthesis directive attribute. Verify the correct directive name. @I:"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_load_store_unit.v" (library work) @N: CG334 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_load_store_unit.v":678:25:678:37|Read directive translate_off. @N: CG333 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_load_store_unit.v":681:25:681:36|Read directive translate_on. @N: CG334 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_load_store_unit.v":811:13:811:25|Read directive translate_off. @N: CG333 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_load_store_unit.v":825:13:825:24|Read directive translate_on. @I:"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_logic_op.v" (library work) @I:"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_shifter.v" (library work) @I:"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_top.v" (library work) @I:"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_monitor.v" (library work) @I:"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_monitor_ram.v" (library work) @N: CG334 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_monitor_ram.v":833:16:833:28|Read directive translate_off. @N: CG333 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_monitor_ram.v":876:16:876:27|Read directive translate_on. @N: CG334 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_monitor_ram.v":953:16:953:28|Read directive translate_off. @N: CG333 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_monitor_ram.v":996:16:996:27|Read directive translate_on. @N: CG334 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_monitor_ram.v":1168:16:1168:28|Read directive translate_off. @N: CG333 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_monitor_ram.v":1243:16:1243:27|Read directive translate_on. @N: CG334 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_monitor_ram.v":1353:16:1353:28|Read directive translate_off. @N: CG333 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_monitor_ram.v":1428:16:1428:27|Read directive translate_on. @N: CG334 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_monitor_ram.v":1697:16:1697:28|Read directive translate_off. @N: CG333 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_monitor_ram.v":1772:16:1772:27|Read directive translate_on. @N: CG334 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_monitor_ram.v":1881:16:1881:28|Read directive translate_off. @N: CG333 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_monitor_ram.v":1956:16:1956:27|Read directive translate_on. @I:"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_ram.v" (library work) @I:"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_trace.v" (library work) @I:"C:\TFG\exp7\mic32\soc\mic32.v":"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v" (library work) @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":252:12:252:18|ipd_idx is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":262:15:262:21|jpd_idx is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":273:15:273:21|kpd_idx is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":284:15:284:21|lpd_idx is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":390:12:390:19|iopd_idx is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":400:15:400:22|jopd_idx is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":411:15:411:22|kopd_idx is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":422:15:422:22|lopd_idx is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":432:12:432:19|mopd_idx is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":442:15:442:22|nopd_idx is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":453:15:453:22|oopd_idx is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":464:15:464:22|popd_idx is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":645:9:645:11|iti is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":672:12:672:14|jti is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":700:12:700:14|kti is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":728:12:728:14|lti is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":1112:12:1112:17|im_idx is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":1122:15:1122:20|jm_idx is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":1133:15:1133:20|km_idx is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":1144:15:1144:20|lm_idx is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":1155:12:1155:18|imb_idx is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":1165:15:1165:21|jmb_idx is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":1176:15:1176:21|kmb_idx is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":1187:15:1187:21|lmb_idx is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":1270:12:1270:12|i is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":1282:15:1282:15|j is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":1295:15:1295:15|k is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":1308:15:1308:15|l is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":1339:19:1339:19|i is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":1363:22:1363:22|j is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":1388:22:1388:22|k is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":1413:22:1413:22|l is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":1440:19:1440:19|i is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":1464:22:1464:22|j is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":1489:22:1489:22|k is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":1514:22:1514:22|l is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":1606:12:1606:19|iitb_idx is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":1618:15:1618:22|jitb_idx is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":1631:15:1631:22|kitb_idx is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":1644:15:1644:22|litb_idx is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":1773:12:1773:17|i_both is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":1796:15:1796:20|j_both is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":1820:15:1820:20|k_both is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":1844:15:1844:20|l_both is already declared in this scope. @I:"C:\TFG\exp7\mic32\soc\mic32.v":"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\tpio.v" (library work) @I:"C:\TFG\exp7\mic32\soc\mic32.v":"C:\TFG\exp7\mic32\soc\../components/asram_top/rtl/verilog\asram_core.v" (library work) @I:"C:\TFG\exp7\mic32\soc\mic32.v":"C:\TFG\exp7\mic32\soc\../components/asram_top/rtl/verilog\asram_top.v" (library work) @I:"C:\TFG\exp7\mic32\soc\mic32.v":"C:\TFG\exp7\mic32\soc\../components/parallel_flash/rtl/verilog\flash_core.v" (library work) @I:"C:\TFG\exp7\mic32\soc\mic32.v":"C:\TFG\exp7\mic32\soc\../components/parallel_flash/rtl/verilog\parallel_flash.v" (library work) Verilog syntax check successful! At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 75MB peak: 77MB) Process completed successfully. # Wed Sep 20 02:06:46 2017 ###########################################################] @I::"C:\lscc\diamond\3.8\synpbase\lib\lucent\machxo2.v" (library work) @I::"C:\lscc\diamond\3.8\synpbase\lib\lucent\pmi_def.v" (library work) @I::"C:\lscc\diamond\3.8\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__) @I::"C:\lscc\diamond\3.8\synpbase\lib\vlog\umr_capim.v" (library snps_haps) @I::"C:\lscc\diamond\3.8\synpbase\lib\vlog\scemi_objects.v" (library snps_haps) @I::"C:\lscc\diamond\3.8\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps) @I::"C:\TFG\exp7\proy_glob\proy_glob.v" (library work) @I::"C:\TFG\exp7\mic32\soc\mic32.v" (library work) @I:"C:\TFG\exp7\mic32\soc\mic32.v":"C:\TFG\exp7\mic32\soc\system_conf.v" (library work) @I:"C:\TFG\exp7\mic32\soc\mic32.v":"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v" (library work) @I:"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\TFG\exp7\mic32\soc\pmi_def.v" (library work) @I:"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\typeb.v" (library work) @I:"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\typea.v" (library work) @I:"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\jtag_cores.v" (library work) @I:"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\jtag_cores.v":"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_include.v" (library work) @I:"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\jtag_lm32.v" (library work) @I:"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_jtag.v" (library work) @I:"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_addsub.v" (library work) @I:"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_adder.v" (library work) @I:"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v" (library work) @W: CS141 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v":652:9:652:17|Unrecognized synthesis directive attribute. Verify the correct directive name. @W: CS141 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v":653:9:653:17|Unrecognized synthesis directive attribute. Verify the correct directive name. @I:"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v":"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_functions.v" (library work) @N: CG334 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v":2773:13:2773:25|Read directive translate_off. @N: CG333 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v":2786:13:2786:24|Read directive translate_on. @I:"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_dcache.v" (library work) @I:"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_debug.v" (library work) @I:"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_decoder.v" (library work) @I:"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_icache.v" (library work) @I:"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_instruction_unit.v" (library work) @I:"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_interrupt.v" (library work) @W: CS141 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_interrupt.v":130:9:130:17|Unrecognized synthesis directive attribute. Verify the correct directive name. @I:"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_load_store_unit.v" (library work) @N: CG334 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_load_store_unit.v":678:25:678:37|Read directive translate_off. @N: CG333 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_load_store_unit.v":681:25:681:36|Read directive translate_on. @N: CG334 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_load_store_unit.v":811:13:811:25|Read directive translate_off. @N: CG333 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_load_store_unit.v":825:13:825:24|Read directive translate_on. @I:"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_logic_op.v" (library work) @I:"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_shifter.v" (library work) @I:"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_top.v" (library work) @I:"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_monitor.v" (library work) @I:"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_monitor_ram.v" (library work) @N: CG334 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_monitor_ram.v":833:16:833:28|Read directive translate_off. @N: CG333 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_monitor_ram.v":876:16:876:27|Read directive translate_on. @N: CG334 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_monitor_ram.v":953:16:953:28|Read directive translate_off. @N: CG333 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_monitor_ram.v":996:16:996:27|Read directive translate_on. @N: CG334 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_monitor_ram.v":1168:16:1168:28|Read directive translate_off. @N: CG333 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_monitor_ram.v":1243:16:1243:27|Read directive translate_on. @N: CG334 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_monitor_ram.v":1353:16:1353:28|Read directive translate_off. @N: CG333 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_monitor_ram.v":1428:16:1428:27|Read directive translate_on. @N: CG334 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_monitor_ram.v":1697:16:1697:28|Read directive translate_off. @N: CG333 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_monitor_ram.v":1772:16:1772:27|Read directive translate_on. @N: CG334 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_monitor_ram.v":1881:16:1881:28|Read directive translate_off. @N: CG333 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_monitor_ram.v":1956:16:1956:27|Read directive translate_on. @I:"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_ram.v" (library work) @I:"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_trace.v" (library work) @I:"C:\TFG\exp7\mic32\soc\mic32.v":"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v" (library work) @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":252:12:252:18|ipd_idx is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":262:15:262:21|jpd_idx is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":273:15:273:21|kpd_idx is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":284:15:284:21|lpd_idx is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":390:12:390:19|iopd_idx is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":400:15:400:22|jopd_idx is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":411:15:411:22|kopd_idx is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":422:15:422:22|lopd_idx is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":432:12:432:19|mopd_idx is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":442:15:442:22|nopd_idx is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":453:15:453:22|oopd_idx is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":464:15:464:22|popd_idx is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":645:9:645:11|iti is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":672:12:672:14|jti is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":700:12:700:14|kti is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":728:12:728:14|lti is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":1112:12:1112:17|im_idx is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":1122:15:1122:20|jm_idx is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":1133:15:1133:20|km_idx is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":1144:15:1144:20|lm_idx is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":1155:12:1155:18|imb_idx is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":1165:15:1165:21|jmb_idx is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":1176:15:1176:21|kmb_idx is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":1187:15:1187:21|lmb_idx is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":1270:12:1270:12|i is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":1282:15:1282:15|j is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":1295:15:1295:15|k is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":1308:15:1308:15|l is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":1339:19:1339:19|i is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":1363:22:1363:22|j is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":1388:22:1388:22|k is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":1413:22:1413:22|l is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":1440:19:1440:19|i is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":1464:22:1464:22|j is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":1489:22:1489:22|k is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":1514:22:1514:22|l is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":1606:12:1606:19|iitb_idx is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":1618:15:1618:22|jitb_idx is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":1631:15:1631:22|kitb_idx is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":1644:15:1644:22|litb_idx is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":1773:12:1773:17|i_both is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":1796:15:1796:20|j_both is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":1820:15:1820:20|k_both is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":1844:15:1844:20|l_both is already declared in this scope. @I:"C:\TFG\exp7\mic32\soc\mic32.v":"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\tpio.v" (library work) @I:"C:\TFG\exp7\mic32\soc\mic32.v":"C:\TFG\exp7\mic32\soc\../components/asram_top/rtl/verilog\asram_core.v" (library work) @I:"C:\TFG\exp7\mic32\soc\mic32.v":"C:\TFG\exp7\mic32\soc\../components/asram_top/rtl/verilog\asram_top.v" (library work) @I:"C:\TFG\exp7\mic32\soc\mic32.v":"C:\TFG\exp7\mic32\soc\../components/parallel_flash/rtl/verilog\flash_core.v" (library work) @I:"C:\TFG\exp7\mic32\soc\mic32.v":"C:\TFG\exp7\mic32\soc\../components/parallel_flash/rtl/verilog\parallel_flash.v" (library work) Verilog syntax check successful! File C:\TFG\exp7\proy_glob\synwork\_verilog_hintfile changed - recompiling File C:\TFG\exp7\mic32\soc\mic32.v changed - recompiling File C:\TFG\exp7\mic32\soc\system_conf.v changed - recompiling File C:\TFG\exp7\mic32\soc\pmi_def.v changed - recompiling File C:\TFG\exp7\mic32\soc\system_conf.v changed - recompiling File C:\TFG\exp7\mic32\soc\system_conf.v changed - recompiling File C:\TFG\exp7\mic32\soc\system_conf.v changed - recompiling File C:\TFG\exp7\mic32\soc\system_conf.v changed - recompiling File C:\TFG\exp7\mic32\soc\system_conf.v changed - recompiling File C:\TFG\exp7\mic32\soc\system_conf.v changed - recompiling File C:\TFG\exp7\mic32\soc\system_conf.v changed - recompiling File C:\TFG\exp7\mic32\soc\system_conf.v changed - recompiling File C:\TFG\exp7\mic32\soc\system_conf.v changed - recompiling File C:\TFG\exp7\mic32\soc\system_conf.v changed - recompiling File C:\TFG\exp7\mic32\soc\system_conf.v changed - recompiling File C:\TFG\exp7\mic32\soc\system_conf.v changed - recompiling @N: CG364 :"C:\lscc\diamond\3.8\synpbase\lib\lucent\machxo2.v":498:7:498:8|Synthesizing module IB in library work. @N: CG364 :"C:\lscc\diamond\3.8\synpbase\lib\lucent\machxo2.v":857:7:857:8|Synthesizing module OB in library work. @N: CG364 :"C:\lscc\diamond\3.8\synpbase\lib\lucent\machxo2.v":1120:7:1120:9|Synthesizing module VHI in library work. @N: CG364 :"C:\TFG\exp7\proy_glob\proy_glob.v":3:7:3:15|Synthesizing module proy_glob in library work. @N: CG794 :"C:\TFG\exp7\proy_glob\proy_glob.v":24:5:24:7|Using module div2 from library work @W: CG781 :"C:\TFG\exp7\proy_glob\proy_glob.v":24:5:24:7|Input Aclr on instance I27 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. @N: CG794 :"C:\TFG\exp7\proy_glob\proy_glob.v":38:10:38:11|Using module mic32_vhd from library work At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 80MB peak: 81MB) Process completed successfully. # Wed Sep 20 02:06:47 2017 ###########################################################] @N: CD720 :"C:\lscc\diamond\3.8\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns @N:"C:\TFG\exp7\div2.vhd":14:7:14:10|Top entity is set to div2. File C:\TFG\exp7\mic32\soc\mic32_vhd.vhd changed - recompiling VHDL syntax check successful! @N: CD630 :"C:\TFG\exp7\mic32\soc\mic32_vhd.vhd":4:7:4:15|Synthesizing work.mic32_vhd.mic32_vhd_a. Post processing for work.mic32_vhd.mic32_vhd_a @N: CD630 :"C:\TFG\exp7\div2.vhd":14:7:14:10|Synthesizing work.div2.structure. Post processing for work.div2.structure At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 70MB) Process completed successfully. # Wed Sep 20 02:06:47 2017 ###########################################################] @I::"C:\lscc\diamond\3.8\synpbase\lib\lucent\machxo2.v" (library work) @I::"C:\lscc\diamond\3.8\synpbase\lib\lucent\pmi_def.v" (library work) @I::"C:\lscc\diamond\3.8\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__) @I::"C:\lscc\diamond\3.8\synpbase\lib\vlog\umr_capim.v" (library snps_haps) @I::"C:\lscc\diamond\3.8\synpbase\lib\vlog\scemi_objects.v" (library snps_haps) @I::"C:\lscc\diamond\3.8\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps) @I::"C:\TFG\exp7\proy_glob\proy_glob.v" (library work) @I::"C:\TFG\exp7\mic32\soc\mic32.v" (library work) @I:"C:\TFG\exp7\mic32\soc\mic32.v":"C:\TFG\exp7\mic32\soc\system_conf.v" (library work) @I:"C:\TFG\exp7\mic32\soc\mic32.v":"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v" (library work) @I:"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\TFG\exp7\mic32\soc\pmi_def.v" (library work) @I:"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\typeb.v" (library work) @I:"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\typea.v" (library work) @I:"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\jtag_cores.v" (library work) @I:"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\jtag_cores.v":"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_include.v" (library work) @I:"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\jtag_lm32.v" (library work) @I:"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_jtag.v" (library work) @I:"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_addsub.v" (library work) @I:"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_adder.v" (library work) @I:"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v" (library work) @W: CS141 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v":652:9:652:17|Unrecognized synthesis directive attribute. Verify the correct directive name. @W: CS141 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v":653:9:653:17|Unrecognized synthesis directive attribute. Verify the correct directive name. @I:"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v":"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_functions.v" (library work) @N: CG334 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v":2773:13:2773:25|Read directive translate_off. @N: CG333 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v":2786:13:2786:24|Read directive translate_on. @I:"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_dcache.v" (library work) @I:"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_debug.v" (library work) @I:"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_decoder.v" (library work) @I:"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_icache.v" (library work) @I:"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_instruction_unit.v" (library work) @I:"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_interrupt.v" (library work) @W: CS141 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_interrupt.v":130:9:130:17|Unrecognized synthesis directive attribute. Verify the correct directive name. @I:"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_load_store_unit.v" (library work) @N: CG334 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_load_store_unit.v":678:25:678:37|Read directive translate_off. @N: CG333 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_load_store_unit.v":681:25:681:36|Read directive translate_on. @N: CG334 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_load_store_unit.v":811:13:811:25|Read directive translate_off. @N: CG333 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_load_store_unit.v":825:13:825:24|Read directive translate_on. @I:"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_logic_op.v" (library work) @I:"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_shifter.v" (library work) @I:"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_top.v" (library work) @I:"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_monitor.v" (library work) @I:"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_monitor_ram.v" (library work) @N: CG334 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_monitor_ram.v":833:16:833:28|Read directive translate_off. @N: CG333 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_monitor_ram.v":876:16:876:27|Read directive translate_on. @N: CG334 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_monitor_ram.v":953:16:953:28|Read directive translate_off. @N: CG333 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_monitor_ram.v":996:16:996:27|Read directive translate_on. @N: CG334 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_monitor_ram.v":1168:16:1168:28|Read directive translate_off. @N: CG333 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_monitor_ram.v":1243:16:1243:27|Read directive translate_on. @N: CG334 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_monitor_ram.v":1353:16:1353:28|Read directive translate_off. @N: CG333 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_monitor_ram.v":1428:16:1428:27|Read directive translate_on. @N: CG334 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_monitor_ram.v":1697:16:1697:28|Read directive translate_off. @N: CG333 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_monitor_ram.v":1772:16:1772:27|Read directive translate_on. @N: CG334 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_monitor_ram.v":1881:16:1881:28|Read directive translate_off. @N: CG333 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_monitor_ram.v":1956:16:1956:27|Read directive translate_on. @I:"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_ram.v" (library work) @I:"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_trace.v" (library work) @I:"C:\TFG\exp7\mic32\soc\mic32.v":"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v" (library work) @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":252:12:252:18|ipd_idx is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":262:15:262:21|jpd_idx is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":273:15:273:21|kpd_idx is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":284:15:284:21|lpd_idx is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":390:12:390:19|iopd_idx is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":400:15:400:22|jopd_idx is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":411:15:411:22|kopd_idx is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":422:15:422:22|lopd_idx is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":432:12:432:19|mopd_idx is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":442:15:442:22|nopd_idx is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":453:15:453:22|oopd_idx is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":464:15:464:22|popd_idx is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":645:9:645:11|iti is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":672:12:672:14|jti is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":700:12:700:14|kti is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":728:12:728:14|lti is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":1112:12:1112:17|im_idx is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":1122:15:1122:20|jm_idx is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":1133:15:1133:20|km_idx is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":1144:15:1144:20|lm_idx is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":1155:12:1155:18|imb_idx is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":1165:15:1165:21|jmb_idx is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":1176:15:1176:21|kmb_idx is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":1187:15:1187:21|lmb_idx is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":1270:12:1270:12|i is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":1282:15:1282:15|j is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":1295:15:1295:15|k is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":1308:15:1308:15|l is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":1339:19:1339:19|i is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":1363:22:1363:22|j is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":1388:22:1388:22|k is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":1413:22:1413:22|l is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":1440:19:1440:19|i is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":1464:22:1464:22|j is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":1489:22:1489:22|k is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":1514:22:1514:22|l is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":1606:12:1606:19|iitb_idx is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":1618:15:1618:22|jitb_idx is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":1631:15:1631:22|kitb_idx is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":1644:15:1644:22|litb_idx is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":1773:12:1773:17|i_both is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":1796:15:1796:20|j_both is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":1820:15:1820:20|k_both is already declared in this scope. @W: CG921 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":1844:15:1844:20|l_both is already declared in this scope. @I:"C:\TFG\exp7\mic32\soc\mic32.v":"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\tpio.v" (library work) @I:"C:\TFG\exp7\mic32\soc\mic32.v":"C:\TFG\exp7\mic32\soc\../components/asram_top/rtl/verilog\asram_core.v" (library work) @I:"C:\TFG\exp7\mic32\soc\mic32.v":"C:\TFG\exp7\mic32\soc\../components/asram_top/rtl/verilog\asram_top.v" (library work) @I:"C:\TFG\exp7\mic32\soc\mic32.v":"C:\TFG\exp7\mic32\soc\../components/parallel_flash/rtl/verilog\flash_core.v" (library work) @I:"C:\TFG\exp7\mic32\soc\mic32.v":"C:\TFG\exp7\mic32\soc\../components/parallel_flash/rtl/verilog\parallel_flash.v" (library work) Verilog syntax check successful! @N: CG364 :"C:\TFG\exp7\mic32\soc\mic32.v":48:7:48:14|Synthesizing module arbiter2 in library work. MAX_DAT_WIDTH=32'b00000000000000000000000000100000 WBS_DAT_WIDTH=32'b00000000000000000000000000100000 WBM0_DAT_WIDTH=32'b00000000000000000000000000100000 WBM1_DAT_WIDTH=32'b00000000000000000000000000100000 Generated name = arbiter2_32s_32s_32s_32s @N: CG364 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_icache.v":86:7:86:17|Synthesizing module lm32_icache in library work. associativity=32'b00000000000000000000000000000001 sets=32'b00000000000000000000000010000000 bytes_per_line=32'b00000000000000000000000000000100 base_address=32'b00000000000000000000000000000000 limit=32'b00000101111111111111111111111111 addr_offset_width=32'b00000000000000000000000000000000 addr_set_width=32'b00000000000000000000000000000111 addr_offset_lsb=32'b00000000000000000000000000000010 addr_offset_msb=32'b00000000000000000000000000000001 addr_set_lsb=32'b00000000000000000000000000000010 addr_set_msb=32'b00000000000000000000000000001000 addr_tag_lsb=32'b00000000000000000000000000001001 addr_tag_msb=32'b00000000000000000000000000011010 addr_tag_width=32'b00000000000000000000000000010010 Generated name = lm32_icache_Z1_layer2 @N: CG364 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_ram.v":61:7:61:14|Synthesizing module lm32_ram in library work. data_width=32'b00000000000000000000000000100000 address_width=32'b00000000000000000000000000000111 RAM_IMPLEMENTATION=32'b01000001010101010101010001001111 RAM_TYPE=48'b010100100100000101001101010111110100010001010000 Generated name = lm32_ram_32s_7s_AUTO_RAM_DP @N: CL134 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_ram.v":297:6:297:11|Found RAM mem, depth=128, width=32 @N: CG364 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_ram.v":61:7:61:14|Synthesizing module lm32_ram in library work. data_width=32'b00000000000000000000000000010011 address_width=32'b00000000000000000000000000000111 RAM_IMPLEMENTATION=32'b01000001010101010101010001001111 RAM_TYPE=48'b010100100100000101001101010111110100010001010000 Generated name = lm32_ram_19s_7s_AUTO_RAM_DP @N: CL134 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_ram.v":297:6:297:11|Found RAM mem, depth=128, width=19 @W: CG133 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_icache.v":197:24:197:40|Object refill_way_select is declared but not assigned. Either assign a value or remove the declaration. @W: CG133 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_icache.v":198:31:198:43|Object refill_offset is declared but not assigned. Either assign a value or remove the declaration. @N: CG364 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_instruction_unit.v":77:7:77:27|Synthesizing module lm32_instruction_unit in library work. associativity=32'b00000000000000000000000000000001 sets=32'b00000000000000000000000010000000 bytes_per_line=32'b00000000000000000000000000000100 base_address=32'b00000000000000000000000000000000 limit=32'b00000101111111111111111111111111 addr_offset_width=32'b00000000000000000000000000000001 addr_offset_lsb=32'b00000000000000000000000000000010 addr_offset_msb=32'b00000000000000000000000000000010 Generated name = lm32_instruction_unit_1s_128s_4s_0_100663295_1s_2s_2s @N: CG793 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_instruction_unit.v":736:16:736:23|Ignoring system task $display @W: CL190 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_instruction_unit.v":677:0:677:5|Optimizing register bit i_adr_o[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W: CL190 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_instruction_unit.v":677:0:677:5|Optimizing register bit i_adr_o[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W: CL190 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_instruction_unit.v":677:0:677:5|Optimizing register bit i_cti_o[0] to a constant 1. To keep the instance, apply constraint syn_preserve=1 on the instance. @W: CL190 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_instruction_unit.v":677:0:677:5|Optimizing register bit i_cti_o[1] to a constant 1. To keep the instance, apply constraint syn_preserve=1 on the instance. @W: CL190 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_instruction_unit.v":677:0:677:5|Optimizing register bit i_cti_o[2] to a constant 1. To keep the instance, apply constraint syn_preserve=1 on the instance. @W: CL190 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_instruction_unit.v":677:0:677:5|Optimizing register bit i_lock_o to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W: CL279 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_instruction_unit.v":677:0:677:5|Pruning register bits 1 to 0 of i_adr_o[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W: CL169 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_instruction_unit.v":677:0:677:5|Pruning unused register i_cti_o[2:0]. Make sure that there are no unused intermediate registers. @W: CL169 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_instruction_unit.v":677:0:677:5|Pruning unused register i_lock_o. Make sure that there are no unused intermediate registers. @N: CG364 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_decoder.v":113:7:113:18|Synthesizing module lm32_decoder in library work. @N: CG364 :"C:\TFG\exp7\mic32\soc\pmi_def.v":94:7:94:21|Synthesizing module pmi_ram_dp_true in library work. pmi_addr_depth_a=32'b00000000000000000000001000000000 pmi_addr_width_a=32'b00000000000000000000000000001001 pmi_data_width_a=32'b00000000000000000000000000100000 pmi_addr_depth_b=32'b00000000000000000000001000000000 pmi_addr_width_b=32'b00000000000000000000000000001001 pmi_data_width_b=32'b00000000000000000000000000100000 pmi_regmode_a=40'b0110111001101111011100100110010101100111 pmi_regmode_b=40'b0110111001101111011100100110010101100111 pmi_gsr=48'b011001010110111001100001011000100110110001100101 pmi_resetmode=32'b01110011011110010110111001100011 pmi_optimization=40'b0111001101110000011001010110010101100100 pmi_init_file=32'b01101110011011110110111001100101 pmi_init_file_format=24'b011010000110010101111000 pmi_write_mode_a=48'b011011100110111101110010011011010110000101101100 pmi_write_mode_b=48'b011011100110111101110010011011010110000101101100 pmi_family=56'b01001101011000010110001101101000010110000100111100110010 module_type=120'b011100000110110101101001010111110111001001100001011011010101111101100100011100000101111101110100011100100111010101100101 Generated name = pmi_ram_dp_true_Z2_layer2 @N: CG364 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_dcache.v":80:7:80:17|Synthesizing module lm32_dcache in library work. associativity=32'b00000000000000000000000000000001 sets=32'b00000000000000000000000010000000 bytes_per_line=32'b00000000000000000000000000000100 base_address=32'b00000000000000000000000000000000 limit=32'b00000101111111111111111111111111 addr_offset_width=32'b00000000000000000000000000000000 addr_set_width=32'b00000000000000000000000000000111 addr_offset_lsb=32'b00000000000000000000000000000010 addr_offset_msb=32'b00000000000000000000000000000001 addr_set_lsb=32'b00000000000000000000000000000010 addr_set_msb=32'b00000000000000000000000000001000 addr_tag_lsb=32'b00000000000000000000000000001001 addr_tag_msb=32'b00000000000000000000000000011010 addr_tag_width=32'b00000000000000000000000000010010 Generated name = lm32_dcache_Z3_layer2 @W: CG133 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_dcache.v":192:24:192:40|Object refill_way_select is declared but not assigned. Either assign a value or remove the declaration. @W: CG133 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_dcache.v":193:31:193:43|Object refill_offset is declared but not assigned. Either assign a value or remove the declaration. @W: CG133 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_dcache.v":197:10:197:10|Object j is declared but not assigned. Either assign a value or remove the declaration. @N: CG364 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_load_store_unit.v":69:7:69:26|Synthesizing module lm32_load_store_unit in library work. associativity=32'b00000000000000000000000000000001 sets=32'b00000000000000000000000010000000 bytes_per_line=32'b00000000000000000000000000000100 base_address=32'b00000000000000000000000000000000 limit=32'b00000101111111111111111111111111 addr_offset_width=32'b00000000000000000000000000000001 addr_offset_lsb=32'b00000000000000000000000000000010 addr_offset_msb=32'b00000000000000000000000000000010 Generated name = lm32_load_store_unit_1s_128s_4s_0_100663295_1s_2s_2s @W: CL190 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_load_store_unit.v":623:0:623:5|Optimizing register bit d_cti_o[0] to a constant 1. To keep the instance, apply constraint syn_preserve=1 on the instance. @W: CL190 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_load_store_unit.v":623:0:623:5|Optimizing register bit d_cti_o[1] to a constant 1. To keep the instance, apply constraint syn_preserve=1 on the instance. @W: CL190 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_load_store_unit.v":623:0:623:5|Optimizing register bit d_cti_o[2] to a constant 1. To keep the instance, apply constraint syn_preserve=1 on the instance. @W: CL190 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_load_store_unit.v":623:0:623:5|Optimizing register bit d_lock_o to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W: CL169 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_load_store_unit.v":623:0:623:5|Pruning unused register d_cti_o[2:0]. Make sure that there are no unused intermediate registers. @W: CL169 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_load_store_unit.v":623:0:623:5|Pruning unused register d_lock_o. Make sure that there are no unused intermediate registers. @N: CG364 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_addsub.v":55:7:55:17|Synthesizing module lm32_addsub in library work. @N: CG364 :"C:\TFG\exp7\mic32\soc\pmi_def.v":48:7:48:16|Synthesizing module pmi_addsub in library work. pmi_data_width=32'b00000000000000000000000000100000 pmi_result_width=32'b00000000000000000000000000100000 pmi_sign=24'b011011110110011001100110 pmi_family=56'b01001101011000010110001101101000010110000100111100110010 module_type=80'b01110000011011010110100101011111011000010110010001100100011100110111010101100010 Generated name = pmi_addsub_32s_32s_off_MachXO2_pmi_addsub @N: CG364 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_adder.v":56:7:56:16|Synthesizing module lm32_adder in library work. @N: CG364 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_logic_op.v":56:7:56:19|Synthesizing module lm32_logic_op in library work. @N: CG364 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_shifter.v":56:7:56:18|Synthesizing module lm32_shifter in library work. @N: CG364 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_interrupt.v":56:7:56:20|Synthesizing module lm32_interrupt in library work. @N: CG364 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_jtag.v":87:7:87:15|Synthesizing module lm32_jtag in library work. @W: CL169 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_jtag.v":309:3:309:8|Pruning unused register command[3:0]. Make sure that there are no unused intermediate registers. @W: CL113 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_jtag.v":309:3:309:8|Feedback mux created for signal state[3:0]. To avoid the feedback mux, assign values explicitly under all conditions of conditional assignment statements. @W: CL250 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_jtag.v":309:3:309:8|All reachable assignments to state[3:0] assign 0, register removed by optimization @N: CG364 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_debug.v":69:7:69:16|Synthesizing module lm32_debug in library work. breakpoints=32'b00000000000000000000000000000000 watchpoints=32'b00000000000000000000000000000000 Generated name = lm32_debug_0s_0 @W: CG133 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_debug.v":164:19:164:22|Object bp_a_-1_ is declared but not assigned. Either assign a value or remove the declaration. @W: CG133 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_debug.v":164:19:164:22|Object bp_a_0_ is declared but not assigned. Either assign a value or remove the declaration. @W: CG133 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_debug.v":165:4:165:7|Object bp_e_-1_ is declared but not assigned. Either assign a value or remove the declaration. @W: CG133 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_debug.v":165:4:165:7|Object bp_e_0_ is declared but not assigned. Either assign a value or remove the declaration. @W: CG360 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_debug.v":166:22:166:31|Removing wire bp_match_n, as there is no assignment to it. @W: CG133 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_debug.v":169:21:169:22|Object wp_-1_ is declared but not assigned. Either assign a value or remove the declaration. @W: CG133 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_debug.v":169:21:169:22|Object wp_0_ is declared but not assigned. Either assign a value or remove the declaration. @W: CG360 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_debug.v":170:20:170:29|Removing wire wp_match_n, as there is no assignment to it. @N: CG364 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v":100:7:100:14|Synthesizing module lm32_cpu in library work. @W: CL169 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v":2303:0:2303:5|Pruning unused register x_result_sel_logic_x. Make sure that there are no unused intermediate registers. @W: CL169 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v":2303:0:2303:5|Pruning unused register eret_m. Make sure that there are no unused intermediate registers. @W: CL169 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v":2303:0:2303:5|Pruning unused register bret_m. Make sure that there are no unused intermediate registers. @N: CG364 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_monitor_ram.v":53:7:53:22|Synthesizing module lm32_monitor_ram in library work. @N: CG364 :"C:\lscc\diamond\3.8\synpbase\lib\lucent\machxo2.v":1291:7:1291:11|Synthesizing module DP8KC in library work. @N: CG364 :"C:\lscc\diamond\3.8\synpbase\lib\lucent\machxo2.v":1120:7:1120:9|Synthesizing module VHI in library work. @N: CG364 :"C:\lscc\diamond\3.8\synpbase\lib\lucent\machxo2.v":1124:7:1124:9|Synthesizing module VLO in library work. @N: CG364 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_monitor.v":57:7:57:18|Synthesizing module lm32_monitor in library work. @A: CL282 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_monitor.v":143:0:143:5|Feedback mux created for signal write_data[31:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area. @N: CG364 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\jtag_cores.v":60:7:60:16|Synthesizing module jtagconn16 in library work. @W: CG146 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\jtag_cores.v":60:7:60:16|Creating black box for empty module jtagconn16 @N: CG364 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\typea.v":65:7:65:11|Synthesizing module TYPEA in library work. @N: CG364 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\jtag_lm32.v":51:7:51:15|Synthesizing module jtag_lm32 in library work. @N: CG364 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\jtag_cores.v":75:29:75:38|Synthesizing module jtag_cores in library work. @W: CG781 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\jtag_cores.v":146:20:146:20|Input CONTROL_DATAN on instance jtag_lm32_inst is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. @N: CG364 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_top.v":58:7:58:14|Synthesizing module lm32_top in library work. @N: CG364 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":80:7:80:10|Synthesizing module gpio in library work. GPIO_WB_DAT_WIDTH=32'b00000000000000000000000000100000 GPIO_WB_ADR_WIDTH=32'b00000000000000000000000000000100 DATA_WIDTH=32'b00000000000000000000000000001000 INPUT_WIDTH=32'b00000000000000000000000000000001 OUTPUT_WIDTH=32'b00000000000000000000000000000001 IRQ_MODE=32'b00000000000000000000000000000000 LEVEL=32'b00000000000000000000000000000000 EDGE=32'b00000000000000000000000000000001 POSE_EDGE_IRQ=32'b00000000000000000000000000000001 NEGE_EDGE_IRQ=32'b00000000000000000000000000000000 EITHER_EDGE_IRQ=32'b00000000000000000000000000000000 INPUT_PORTS_ONLY=32'b00000000000000000000000000000000 OUTPUT_PORTS_ONLY=32'b00000000000000000000000000000001 BOTH_INPUT_AND_OUTPUT=32'b00000000000000000000000000000000 TRISTATE_PORTS=32'b00000000000000000000000000000000 UDLY=32'b00000000000000000000000000000001 Generated name = gpio_Z4_layer2 @N: CG364 :"C:\lscc\diamond\3.8\synpbase\lib\lucent\machxo2.v":82:7:82:8|Synthesizing module BB in library work. @N: CG364 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\tpio.v":66:7:66:10|Synthesizing module tpio in library work. DATA_WIDTH=32'b00000000000000000000000000000001 IRQ_MODE=32'b00000000000000000000000000000000 LEVEL=32'b00000000000000000000000000000000 EDGE=32'b00000000000000000000000000000001 POSE_EDGE_IRQ=32'b00000000000000000000000000000001 NEGE_EDGE_IRQ=32'b00000000000000000000000000000000 EITHER_EDGE_IRQ=32'b00000000000000000000000000000000 UDLY=32'b00000000000000000000000000000001 Generated name = tpio_1s_0s_0s_1s_1s_0s_0s_1s @W: CG133 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\tpio.v":109:9:109:16|Object IRQ_MASK is declared but not assigned. Either assign a value or remove the declaration. @W: CG133 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\tpio.v":110:9:110:16|Object IRQ_TEMP is declared but not assigned. Either assign a value or remove the declaration. @W: CG133 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\tpio.v":111:9:111:20|Object EDGE_CAPTURE is declared but not assigned. Either assign a value or remove the declaration. @W: CG133 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\tpio.v":112:9:112:20|Object PIO_DATA_DLY is declared but not assigned. Either assign a value or remove the declaration. @W: CG360 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":124:30:124:41|Removing wire PIO_BOTH_OUT, as there is no assignment to it. @W: CG133 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":145:26:145:34|Object PIO_DATAO is declared but not assigned. Either assign a value or remove the declaration. @W: CG133 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":146:26:146:34|Object PIO_DATAI is declared but not assigned. Either assign a value or remove the declaration. @W: CG360 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":151:12:151:27|Removing wire PIO_DATA_WR_EN_0, as there is no assignment to it. @W: CG360 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":151:30:151:45|Removing wire PIO_DATA_WR_EN_1, as there is no assignment to it. @W: CG360 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":151:48:151:63|Removing wire PIO_DATA_WR_EN_2, as there is no assignment to it. @W: CG360 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":151:66:151:81|Removing wire PIO_DATA_WR_EN_3, as there is no assignment to it. @W: CG360 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":154:12:154:26|Removing wire PIO_TRI_WR_EN_0, as there is no assignment to it. @W: CG360 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":154:29:154:43|Removing wire PIO_TRI_WR_EN_1, as there is no assignment to it. @W: CG360 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":154:46:154:60|Removing wire PIO_TRI_WR_EN_2, as there is no assignment to it. @W: CG360 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":154:63:154:77|Removing wire PIO_TRI_WR_EN_3, as there is no assignment to it. @W: CG360 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":157:12:157:27|Removing wire IRQ_MASK_WR_EN_0, as there is no assignment to it. @W: CG360 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":157:30:157:45|Removing wire IRQ_MASK_WR_EN_1, as there is no assignment to it. @W: CG360 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":157:48:157:63|Removing wire IRQ_MASK_WR_EN_2, as there is no assignment to it. @W: CG360 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":157:66:157:81|Removing wire IRQ_MASK_WR_EN_3, as there is no assignment to it. @W: CG360 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":160:12:160:27|Removing wire EDGE_CAP_WR_EN_0, as there is no assignment to it. @W: CG360 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":160:30:160:45|Removing wire EDGE_CAP_WR_EN_1, as there is no assignment to it. @W: CG360 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":160:48:160:63|Removing wire EDGE_CAP_WR_EN_2, as there is no assignment to it. @W: CG360 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":160:66:160:81|Removing wire EDGE_CAP_WR_EN_3, as there is no assignment to it. @W: CG133 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":167:26:167:33|Object IRQ_MASK is declared but not assigned. Either assign a value or remove the declaration. @W: CG133 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":168:26:168:38|Object IRQ_MASK_BOTH is declared but not assigned. Either assign a value or remove the declaration. @W: CG133 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":169:26:169:33|Object IRQ_TEMP is declared but not assigned. Either assign a value or remove the declaration. @W: CG133 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":170:26:170:38|Object IRQ_TEMP_BOTH is declared but not assigned. Either assign a value or remove the declaration. @W: CG133 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":171:26:171:37|Object EDGE_CAPTURE is declared but not assigned. Either assign a value or remove the declaration. @W: CG133 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":172:26:172:42|Object EDGE_CAPTURE_BOTH is declared but not assigned. Either assign a value or remove the declaration. @W: CG133 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":173:26:173:37|Object PIO_DATA_DLY is declared but not assigned. Either assign a value or remove the declaration. @W: CG133 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":174:26:174:42|Object PIO_DATA_DLY_BOTH is declared but not assigned. Either assign a value or remove the declaration. @W: CG133 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":262:15:262:21|Object jpd_idx is declared but not assigned. Either assign a value or remove the declaration. @W: CG133 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":273:15:273:21|Object kpd_idx is declared but not assigned. Either assign a value or remove the declaration. @W: CG133 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":284:15:284:21|Object lpd_idx is declared but not assigned. Either assign a value or remove the declaration. @W: CG133 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":390:12:390:19|Object iopd_idx is declared but not assigned. Either assign a value or remove the declaration. @W: CG133 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":400:15:400:22|Object jopd_idx is declared but not assigned. Either assign a value or remove the declaration. @W: CG133 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":411:15:411:22|Object kopd_idx is declared but not assigned. Either assign a value or remove the declaration. @W: CG133 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":422:15:422:22|Object lopd_idx is declared but not assigned. Either assign a value or remove the declaration. @W: CG133 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":432:12:432:19|Object mopd_idx is declared but not assigned. Either assign a value or remove the declaration. @W: CG133 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":442:15:442:22|Object nopd_idx is declared but not assigned. Either assign a value or remove the declaration. @W: CG133 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":453:15:453:22|Object oopd_idx is declared but not assigned. Either assign a value or remove the declaration. @W: CG133 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":464:15:464:22|Object popd_idx is declared but not assigned. Either assign a value or remove the declaration. @W: CG133 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":672:12:672:14|Object jti is declared but not assigned. Either assign a value or remove the declaration. @W: CG133 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":700:12:700:14|Object kti is declared but not assigned. Either assign a value or remove the declaration. @W: CG133 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":728:12:728:14|Object lti is declared but not assigned. Either assign a value or remove the declaration. @W: CG133 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":1112:12:1112:17|Object im_idx is declared but not assigned. Either assign a value or remove the declaration. @W: CG133 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":1122:15:1122:20|Object jm_idx is declared but not assigned. Either assign a value or remove the declaration. @W: CG133 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":1133:15:1133:20|Object km_idx is declared but not assigned. Either assign a value or remove the declaration. @W: CG133 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":1144:15:1144:20|Object lm_idx is declared but not assigned. Either assign a value or remove the declaration. @W: CG133 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":1155:12:1155:18|Object imb_idx is declared but not assigned. Either assign a value or remove the declaration. @W: CG133 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":1165:15:1165:21|Object jmb_idx is declared but not assigned. Either assign a value or remove the declaration. @W: CG133 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":1176:15:1176:21|Object kmb_idx is declared but not assigned. Either assign a value or remove the declaration. @W: CG133 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":1187:15:1187:21|Object lmb_idx is declared but not assigned. Either assign a value or remove the declaration. @W: CG133 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":1440:19:1440:19|Object i is declared but not assigned. Either assign a value or remove the declaration. @W: CG133 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":1464:22:1464:22|Object j is declared but not assigned. Either assign a value or remove the declaration. @W: CG133 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":1489:22:1489:22|Object k is declared but not assigned. Either assign a value or remove the declaration. @W: CG133 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":1514:22:1514:22|Object l is declared but not assigned. Either assign a value or remove the declaration. @W: CG133 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":1606:12:1606:19|Object iitb_idx is declared but not assigned. Either assign a value or remove the declaration. @W: CG133 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":1618:15:1618:22|Object jitb_idx is declared but not assigned. Either assign a value or remove the declaration. @W: CG133 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":1631:15:1631:22|Object kitb_idx is declared but not assigned. Either assign a value or remove the declaration. @W: CG133 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":1644:15:1644:22|Object litb_idx is declared but not assigned. Either assign a value or remove the declaration. @W: CG133 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":1773:12:1773:17|Object i_both is declared but not assigned. Either assign a value or remove the declaration. @W: CG133 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":1796:15:1796:20|Object j_both is declared but not assigned. Either assign a value or remove the declaration. @W: CG133 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":1820:15:1820:20|Object k_both is declared but not assigned. Either assign a value or remove the declaration. @W: CG133 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":1844:15:1844:20|Object l_both is declared but not assigned. Either assign a value or remove the declaration. @N: CG364 :"C:\TFG\exp7\mic32\soc\../components/asram_top/rtl/verilog\asram_core.v":66:7:66:16|Synthesizing module asram_core in library work. WB_DAT_WIDTH=32'b00000000000000000000000000100000 SRAM_DATA_WIDTH=32'b00000000000000000000000000100000 SRAM_ADDR_WIDTH=32'b00000000000000000000000000010111 SRAM_BE_WIDTH=32'b00000000000000000000000000000100 READ_LATENCY=32'b00000000000000000000000000000001 WRITE_LATENCY=32'b00000000000000000000000000000001 DATA_OUTPUT_REG=32'b00000000000000000000000000000001 SM_IDLE=2'b00 SM_BUSY=2'b01 SM_WAIT=2'b10 Generated name = asram_core_32s_32s_23s_4s_1s_1s_1s_0_1_2 @W: CG133 :"C:\TFG\exp7\mic32\soc\../components/asram_top/rtl/verilog\asram_core.v":109:20:109:25|Object acycle is declared but not assigned. Either assign a value or remove the declaration. @W: CG133 :"C:\TFG\exp7\mic32\soc\../components/asram_top/rtl/verilog\asram_core.v":109:28:109:40|Object cycle_counter is declared but not assigned. Either assign a value or remove the declaration. @W: CG133 :"C:\TFG\exp7\mic32\soc\../components/asram_top/rtl/verilog\asram_core.v":109:43:109:59|Object cycle_counter_nxt is declared but not assigned. Either assign a value or remove the declaration. @W: CL190 :"C:\TFG\exp7\mic32\soc\../components/asram_top/rtl/verilog\asram_core.v":446:7:446:12|Optimizing register bit genblk2.genblk1.sram_addr[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W: CL190 :"C:\TFG\exp7\mic32\soc\../components/asram_top/rtl/verilog\asram_core.v":446:7:446:12|Optimizing register bit genblk2.genblk1.sram_addr[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W: CL279 :"C:\TFG\exp7\mic32\soc\../components/asram_top/rtl/verilog\asram_core.v":446:7:446:12|Pruning register bits 1 to 0 of genblk2.genblk1.sram_addr[22:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @N: CG364 :"C:\TFG\exp7\mic32\soc\../components/asram_top/rtl/verilog\asram_top.v":58:7:58:15|Synthesizing module asram_top in library work. ASRAM_WB_DAT_WIDTH=32'b00000000000000000000000000100000 SRAM_DATA_WIDTH=32'b00000000000000000000000000100000 SRAM_ADDR_WIDTH=32'b00000000000000000000000000010111 SRAM_BE_WIDTH=32'b00000000000000000000000000000100 READ_LATENCY=32'b00000000000000000000000000000001 WRITE_LATENCY=32'b00000000000000000000000000000001 DATA_OUTPUT_REG=32'b00000000000000000000000000000001 Generated name = asram_top_32s_32s_23s_4s_1s_1s_1s @N: CG364 :"C:\TFG\exp7\mic32\soc\../components/parallel_flash/rtl/verilog\flash_core.v":63:7:63:16|Synthesizing module flash_core in library work. SRAM_DATA_WIDTH=32'b00000000000000000000000000100000 SRAM_ADDR_WIDTH=32'b00000000000000000000000000011001 READ_LATENCY=32'b00000000000000000000000000000111 WRITE_LATENCY=32'b00000000000000000000000000000111 SRAM_CYCLE=32'b00000000000000000000000000000001 SRAM_BE_WIDTH=32'b00000000000000000000000000000100 Generated name = flash_core_32s_25s_7s_7s_1s_4s @N: CG364 :"C:\TFG\exp7\mic32\soc\../components/parallel_flash/rtl/verilog\parallel_flash.v":62:7:62:20|Synthesizing module parallel_flash in library work. SRAM_DATA_WIDTH=32'b00000000000000000000000000100000 SRAM_ADDR_WIDTH=32'b00000000000000000000000000011001 SRAM_BE_WIDTH=32'b00000000000000000000000000000100 READ_LATENCY=32'b00000000000000000000000000000111 WRITE_LATENCY=32'b00000000000000000000000000000111 FLASH_SIGNALS=32'b00000000000000000000000000000001 FLASH_BYTE=32'b00000000000000000000000000000000 FLASH_WP=32'b00000000000000000000000000000000 FLASH_RST=32'b00000000000000000000000000000000 FLASH_BYTEN=32'b00000000000000000000000000000001 FLASH_WPN=32'b00000000000000000000000000000001 FLASH_RSTN=32'b00000000000000000000000000000001 Generated name = parallel_flash_Z5_layer2 @N: CG364 :"C:\TFG\exp7\mic32\soc\mic32.v":336:7:336:11|Synthesizing module mic32 in library work. @W: CG781 :"C:\TFG\exp7\mic32\soc\mic32.v":629:1:629:3|Input PIO_IN on instance LED is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. @W: CG781 :"C:\TFG\exp7\mic32\soc\mic32.v":629:1:629:3|Input PIO_BOTH_IN on instance LED is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. @W: CG360 :"C:\TFG\exp7\mic32\soc\mic32.v":375:5:375:16|Removing wire SHAREDBUS_en, as there is no assignment to it. @N: CL159 :"C:\TFG\exp7\mic32\soc\../components/parallel_flash/rtl/verilog\parallel_flash.v":120:14:120:25|Input ASRAM_LOCK_I is unused. @N: CL201 :"C:\TFG\exp7\mic32\soc\../components/parallel_flash/rtl/verilog\flash_core.v":146:3:146:8|Trying to extract state machine for register main_sm. Extracted state machine for register main_sm State machine has 7 reachable states with original encodings of: 000 001 010 011 100 101 110 @W: CL246 :"C:\TFG\exp7\mic32\soc\../components/parallel_flash/rtl/verilog\flash_core.v":101:30:101:35|Input port bits 31 to 25 of addr_i[31:0] are unused. Assign logic for all port bits or change the input port size. @N: CL159 :"C:\TFG\exp7\mic32\soc\../components/parallel_flash/rtl/verilog\flash_core.v":100:30:100:34|Input bte_i is unused. @N: CL159 :"C:\TFG\exp7\mic32\soc\../components/asram_top/rtl/verilog\asram_top.v":81:10:81:21|Input ASRAM_LOCK_I is unused. @N: CL201 :"C:\TFG\exp7\mic32\soc\../components/asram_top/rtl/verilog\asram_core.v":162:3:162:8|Trying to extract state machine for register state. Extracted state machine for register state State machine has 3 reachable states with original encodings of: 00 01 10 @W: CL246 :"C:\TFG\exp7\mic32\soc\../components/asram_top/rtl/verilog\asram_core.v":84:17:84:22|Input port bits 31 to 23 of addr_i[31:0] are unused. Assign logic for all port bits or change the input port size. @W: CL246 :"C:\TFG\exp7\mic32\soc\../components/asram_top/rtl/verilog\asram_core.v":84:17:84:22|Input port bits 1 to 0 of addr_i[31:0] are unused. Assign logic for all port bits or change the input port size. @N: CL159 :"C:\TFG\exp7\mic32\soc\../components/asram_top/rtl/verilog\asram_core.v":83:16:83:20|Input bte_i is unused. @A: CL153 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\tpio.v":109:9:109:16|*Unassigned bits of IRQ_MASK are referenced and tied to 0 -- simulation mismatch possible. @N: CL159 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\tpio.v":98:10:98:23|Input IRQ_MASK_WR_EN is unused. @N: CL159 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\tpio.v":99:10:99:23|Input EDGE_CAP_WR_EN is unused. @W: CL246 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":110:34:110:43|Input port bits 1 to 0 of GPIO_ADR_I[3:0] are unused. Assign logic for all port bits or change the input port size. @W: CL246 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":111:34:111:43|Input port bits 23 to 0 of GPIO_DAT_I[31:0] are unused. Assign logic for all port bits or change the input port size. @W: CL246 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":112:36:112:45|Input port bits 2 to 0 of GPIO_SEL_I[3:0] are unused. Assign logic for all port bits or change the input port size. @W: CL157 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":124:30:124:41|*Output PIO_BOTH_OUT has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @N: CL159 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":104:10:104:19|Input GPIO_CYC_I is unused. @N: CL159 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":107:10:107:20|Input GPIO_LOCK_I is unused. @N: CL159 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":108:16:108:25|Input GPIO_CTI_I is unused. @N: CL159 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":109:16:109:25|Input GPIO_BTE_I is unused. @N: CL159 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":121:27:121:32|Input PIO_IN is unused. @N: CL159 :"C:\TFG\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":122:28:122:38|Input PIO_BOTH_IN is unused. @W: CL246 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_top.v":168:23:168:33|Input port bits 31 to 14 of DEBUG_ADR_I[31:0] are unused. Assign logic for all port bits or change the input port size. @W: CL246 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_top.v":168:23:168:33|Input port bits 12 to 11 of DEBUG_ADR_I[31:0] are unused. Assign logic for all port bits or change the input port size. @W: CL246 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_top.v":168:23:168:33|Input port bits 1 to 0 of DEBUG_ADR_I[31:0] are unused. Assign logic for all port bits or change the input port size. @N: CL159 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_top.v":172:24:172:34|Input DEBUG_CTI_I is unused. @N: CL159 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_top.v":173:24:173:34|Input DEBUG_BTE_I is unused. @N: CL159 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_top.v":174:6:174:17|Input DEBUG_LOCK_I is unused. @N: CL159 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\jtag_lm32.v":60:13:60:25|Input CONTROL_DATAN is unused. @N: CL201 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_monitor.v":143:0:143:5|Trying to extract state machine for register state. Extracted state machine for register state State machine has 3 reachable states with original encodings of: 00 01 10 @N: CL134 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v":2664:0:2664:5|Found RAM registers, depth=32, width=32 @N: CL134 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v":2664:0:2664:5|Found RAM registers, depth=32, width=32 @N: CL159 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v":279:6:279:12|Input I_RTY_I is unused. @W: CL246 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_debug.v":123:23:123:36|Input port bits 31 to 2 of csr_write_data[31:0] are unused. Assign logic for all port bits or change the input port size. @W: CL247 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_debug.v":123:23:123:36|Input port bit 0 of csr_write_data[31:0] is unused @N: CL159 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_debug.v":118:21:118:24|Input pc_x is unused. @N: CL159 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_debug.v":119:6:119:11|Input load_x is unused. @N: CL159 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_debug.v":120:6:120:12|Input store_x is unused. @N: CL159 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_debug.v":121:23:121:42|Input load_store_address_x is unused. @W: CL246 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_jtag.v":151:26:151:39|Input port bits 31 to 8 of csr_write_data[31:0] are unused. Assign logic for all port bits or change the input port size. @N: CL159 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_jtag.v":139:9:139:16|Input jtag_clk is unused. @W: CL246 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_shifter.v":79:23:79:33|Input port bits 31 to 5 of operand_1_x[31:0] are unused. Assign logic for all port bits or change the input port size. @N: CL159 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_load_store_unit.v":165:6:165:14|Input store_q_x is unused. @N: CL159 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_load_store_unit.v":182:6:182:12|Input d_rty_i is unused. @N: CL201 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_dcache.v":464:0:464:5|Trying to extract state machine for register state. Extracted state machine for register state State machine has 3 reachable states with original encodings of: 001 010 100 @W: CL246 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_dcache.v":136:23:136:31|Input port bits 31 to 9 of address_x[31:0] are unused. Assign logic for all port bits or change the input port size. @W: CL246 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_dcache.v":136:23:136:31|Input port bits 1 to 0 of address_x[31:0] are unused. Assign logic for all port bits or change the input port size. @N: CL159 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_ram.v":92:9:92:13|Input reset is unused. @N: CL159 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_ram.v":92:9:92:13|Input reset is unused. @N: CL201 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_icache.v":403:0:403:5|Trying to extract state machine for register state. Extracted state machine for register state State machine has 4 reachable states with original encodings of: 0001 0010 0100 1000 @W: CL246 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_icache.v":145:21:145:29|Input port bits 31 to 9 of address_a[31:2] are unused. Assign logic for all port bits or change the input port size. @N: CL201 :"C:\TFG\exp7\mic32\soc\mic32.v":246:0:246:5|Trying to extract state machine for register selected. Extracted state machine for register selected State machine has 3 reachable states with original encodings of: 00 01 10 At c_ver Exit (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 103MB peak: 116MB) Process completed successfully. # Wed Sep 20 02:06:51 2017 ###########################################################] Synopsys Netlist Linker, version comp2016q2rc, Build 192R, built Jul 5 2016 @N|Running in 64-bit mode File C:\TFG\exp7\proy_glob\synwork\layer0.srs changed - recompiling File C:\TFG\exp7\proy_glob\synwork\layer1.srs changed - recompiling File C:\TFG\exp7\proy_glob\synwork\layer2.srs changed - recompiling @W: Z198 :"C:\TFG\exp7\mic32\soc\../components/lm32_top/rtl/verilog\jtag_cores.v":126:70:126:89|Unbound component jtagconn16 of instance jtagconn16_lm32_inst @W: Z198 :"C:\TFG\exp7\div2.vhd":60:4:60:7|Unbound component FD1P3DX of instance FF_0 @W: Z198 :"C:\TFG\exp7\div2.vhd":67:4:67:10|Unbound component FADD2B of instance cnt_cia @W: Z198 :"C:\TFG\exp7\div2.vhd":72:4:72:8|Unbound component CU2 of instance cnt_0 ======================================================================================= For a summary of linker messages for components that did not bind, please see log file: @L: C:\TFG\exp7\proy_glob\synwork\proy_glob_proy_glob_comp.linkerlog ======================================================================================= At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 73MB peak: 73MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Wed Sep 20 02:06:52 2017 ###########################################################] @END At c_hdl Exit (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:05s; Memory used current: 4MB peak: 5MB) Process took 0h:00m:06s realtime, 0h:00m:05s cputime Process completed successfully. # Wed Sep 20 02:06:52 2017 ###########################################################] Synopsys Netlist Linker, version comp2016q2rc, Build 192R, built Jul 5 2016 @N|Running in 64-bit mode File C:\TFG\exp7\proy_glob\synwork\proy_glob_proy_glob_comp.srs changed - recompiling At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 76MB peak: 77MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Wed Sep 20 02:06:54 2017 ###########################################################] Pre-mapping Report Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1498R, Built Jul 5 2016 10:30:31 Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Product Version L-2016.03L-1 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB) @A: MF827 |No constraint file specified. @L: C:\TFG\exp7\proy_glob\proy_glob_proy_glob_scck.rpt Printing clock summary report in "C:\TFG\exp7\proy_glob\proy_glob_proy_glob_scck.rpt" file @N: MF248 |Running in 64-bit mode. @N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 112MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 112MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 120MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 122MB) @W: BN132 :"c:\tfg\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_instruction_unit.v":677:0:677:5|Removing sequential instance I1.lm32_inst.LM32.cpu.instruction_unit.i_stb_o because it is equivalent to instance I1.lm32_inst.LM32.cpu.instruction_unit.i_cyc_o. To keep the instance, apply constraint syn_preserve=1 on the instance. @W: BN132 :"c:\tfg\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_load_store_unit.v":623:0:623:5|Removing sequential instance I1.lm32_inst.LM32.cpu.load_store_unit.d_stb_o because it is equivalent to instance I1.lm32_inst.LM32.cpu.load_store_unit.d_cyc_o. To keep the instance, apply constraint syn_preserve=1 on the instance. ICG Latch Removal Summary: Number of ICG latches removed: 0 Number of ICG latches not removed: 0 syn_allowed_resources : blockrams=26 set on top level netlist proy_glob Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 149MB peak: 150MB) Clock Summary ***************** Start Requested Requested Clock Clock Clock Clock Frequency Period Type Group Load -------------------------------------------------------------------------------------------------------------------------------------- System 1.0 MHz 1000.000 system system_clkgroup 0 div2|tdataout0_derived_clock 1.0 MHz 1000.000 derived (from proy_glob|sal_osc) Inferred_clkgroup_0 1577 jtag_cores|jtck 1.0 MHz 1000.000 inferred Inferred_clkgroup_1 22 jtag_lm32|REG_UPDATE_inferred_clock 1.0 MHz 1000.000 inferred Inferred_clkgroup_2 1 proy_glob|sal_osc 1.0 MHz 1000.000 inferred Inferred_clkgroup_0 1 ====================================================================================================================================== @W: MT529 :"c:\tfg\exp7\div2.vhd":60:4:60:7|Found inferred clock proy_glob|sal_osc which controls 1 sequential elements including I27.FF_0. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. @W: MT529 :"c:\tfg\exp7\mic32\soc\../components/lm32_top/rtl/verilog\typea.v":94:2:94:7|Found inferred clock jtag_cores|jtck which controls 22 sequential elements including I1.lm32_inst.LM32.jtag_cores.jtag_lm32_inst.DATA_BIT0.DATA_OUT. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. @W: MT529 :"c:\tfg\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_jtag.v":274:3:274:8|Found inferred clock jtag_lm32|REG_UPDATE_inferred_clock which controls 1 sequential elements including I1.lm32_inst.LM32.cpu.jtag.rx_toggle. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. Finished Pre Mapping Phase. Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 147MB peak: 150MB) Encoding state machine selected[2:0] (in view: work.arbiter2_32s_32s_32s_32s(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 Encoding state machine state[3:0] (in view: work.lm32_icache_Z1_layer2(verilog)) original code -> new code 0001 -> 00 0010 -> 01 0100 -> 10 1000 -> 11 @N: MO225 :"c:\tfg\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_icache.v":403:0:403:5|There are no possible illegal states for state machine state[3:0] (in view: work.lm32_icache_Z1_layer2(verilog)); safe FSM implementation is not required. Encoding state machine state[2:0] (in view: work.lm32_dcache_Z3_layer2(verilog)) original code -> new code 001 -> 00 010 -> 01 100 -> 10 Encoding state machine state[2:0] (in view: work.lm32_monitor(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 Encoding state machine state[2:0] (in view: work.asram_core_32s_32s_23s_4s_1s_1s_1s_0_1_2(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 Encoding state machine main_sm[6:0] (in view: work.flash_core_32s_25s_7s_7s_1s_4s(verilog)) original code -> new code 000 -> 0000001 001 -> 0000010 010 -> 0000100 011 -> 0001000 100 -> 0010000 101 -> 0100000 110 -> 1000000 @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_dcache.v":464:0:464:5|Removing sequential instance refill_address[1] (in view: work.lm32_dcache_Z3_layer2(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_dcache.v":464:0:464:5|Removing sequential instance refill_address[0] (in view: work.lm32_dcache_Z3_layer2(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. None None Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 149MB peak: 151MB) Pre-mapping successful! At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 64MB peak: 151MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Wed Sep 20 02:06:56 2017 ###########################################################] Map & Optimize Report Synopsys Lattice Technology Mapper, Version maplat, Build 1498R, Built Jul 5 2016 10:30:31 Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Product Version L-2016.03L-1 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB) @N: MF248 |Running in 64-bit mode. @N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 111MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 113MB) Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 146MB) @N: MO111 :"c:\tfg\exp7\mic32\soc\../components/gpio/rtl/verilog\gpio.v":124:30:124:41|Tristate driver PIO_BOTH_OUT_1 (in view: work.gpio_Z4_layer2(verilog)) on net PIO_BOTH_OUT_1 (in view: work.gpio_Z4_layer2(verilog)) has its enable tied to GND. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/gpio/rtl/verilog\tpio.v":126:3:126:8|Removing sequential instance genblk9\.itio_inst\[3\]\.TP.PIO_DATA_I (in view: work.gpio_Z4_layer2(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/gpio/rtl/verilog\tpio.v":126:3:126:8|Removing sequential instance genblk9\.itio_inst\[6\]\.TP.PIO_DATA_I (in view: work.gpio_Z4_layer2(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/gpio/rtl/verilog\tpio.v":126:3:126:8|Removing sequential instance genblk9\.itio_inst\[0\]\.TP.PIO_DATA_I (in view: work.gpio_Z4_layer2(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/gpio/rtl/verilog\tpio.v":126:3:126:8|Removing sequential instance genblk9\.itio_inst\[7\]\.TP.PIO_DATA_I (in view: work.gpio_Z4_layer2(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/gpio/rtl/verilog\tpio.v":126:3:126:8|Removing sequential instance genblk9\.itio_inst\[2\]\.TP.PIO_DATA_I (in view: work.gpio_Z4_layer2(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/gpio/rtl/verilog\tpio.v":126:3:126:8|Removing sequential instance genblk9\.itio_inst\[4\]\.TP.PIO_DATA_I (in view: work.gpio_Z4_layer2(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/gpio/rtl/verilog\tpio.v":126:3:126:8|Removing sequential instance genblk9\.itio_inst\[1\]\.TP.PIO_DATA_I (in view: work.gpio_Z4_layer2(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/gpio/rtl/verilog\tpio.v":126:3:126:8|Removing sequential instance genblk9\.itio_inst\[5\]\.TP.PIO_DATA_I (in view: work.gpio_Z4_layer2(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/gpio/rtl/verilog\tpio.v":120:3:120:8|Removing sequential instance LED.genblk9\.itio_inst\[3\]\.TP.PIO_DATA_O (in view: work.mic32(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/gpio/rtl/verilog\tpio.v":114:3:114:8|Removing sequential instance LED.genblk9\.itio_inst\[3\]\.TP.PIO_TRI (in view: work.mic32(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/gpio/rtl/verilog\tpio.v":120:3:120:8|Removing sequential instance LED.genblk9\.itio_inst\[6\]\.TP.PIO_DATA_O (in view: work.mic32(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/gpio/rtl/verilog\tpio.v":114:3:114:8|Removing sequential instance LED.genblk9\.itio_inst\[6\]\.TP.PIO_TRI (in view: work.mic32(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/gpio/rtl/verilog\tpio.v":120:3:120:8|Removing sequential instance LED.genblk9\.itio_inst\[0\]\.TP.PIO_DATA_O (in view: work.mic32(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/gpio/rtl/verilog\tpio.v":114:3:114:8|Removing sequential instance LED.genblk9\.itio_inst\[0\]\.TP.PIO_TRI (in view: work.mic32(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/gpio/rtl/verilog\tpio.v":120:3:120:8|Removing sequential instance LED.genblk9\.itio_inst\[7\]\.TP.PIO_DATA_O (in view: work.mic32(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/gpio/rtl/verilog\tpio.v":114:3:114:8|Removing sequential instance LED.genblk9\.itio_inst\[7\]\.TP.PIO_TRI (in view: work.mic32(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/gpio/rtl/verilog\tpio.v":120:3:120:8|Removing sequential instance LED.genblk9\.itio_inst\[2\]\.TP.PIO_DATA_O (in view: work.mic32(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/gpio/rtl/verilog\tpio.v":114:3:114:8|Removing sequential instance LED.genblk9\.itio_inst\[2\]\.TP.PIO_TRI (in view: work.mic32(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/gpio/rtl/verilog\tpio.v":120:3:120:8|Removing sequential instance LED.genblk9\.itio_inst\[4\]\.TP.PIO_DATA_O (in view: work.mic32(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/gpio/rtl/verilog\tpio.v":114:3:114:8|Removing sequential instance LED.genblk9\.itio_inst\[4\]\.TP.PIO_TRI (in view: work.mic32(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/gpio/rtl/verilog\tpio.v":120:3:120:8|Removing sequential instance LED.genblk9\.itio_inst\[1\]\.TP.PIO_DATA_O (in view: work.mic32(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/gpio/rtl/verilog\tpio.v":114:3:114:8|Removing sequential instance LED.genblk9\.itio_inst\[1\]\.TP.PIO_TRI (in view: work.mic32(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/gpio/rtl/verilog\tpio.v":120:3:120:8|Removing sequential instance LED.genblk9\.itio_inst\[5\]\.TP.PIO_DATA_O (in view: work.mic32(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/gpio/rtl/verilog\tpio.v":114:3:114:8|Removing sequential instance LED.genblk9\.itio_inst\[5\]\.TP.PIO_TRI (in view: work.mic32(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @W: BN132 :"c:\tfg\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_ram.v":302:6:302:11|Removing sequential instance I1.lm32_inst.LM32.cpu.instruction_unit.icache.memories[0].way_0_data_ram.genblk1.ra[6:0] because it is equivalent to instance I1.lm32_inst.LM32.cpu.instruction_unit.icache.memories[0].way_0_tag_ram.genblk1.ra[6:0]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W: BN132 :"c:\tfg\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_ram.v":302:6:302:11|Removing sequential instance I1.lm32_inst.LM32.cpu.load_store_unit.dcache.memories[0].data_memories.way_0_data_ram.genblk1.ra[6:0] because it is equivalent to instance I1.lm32_inst.LM32.cpu.load_store_unit.dcache.memories[0].way_0_tag_ram.genblk1.ra[6:0]. To keep the instance, apply constraint syn_preserve=1 on the instance. Available hyper_sources - for debug and ip models None Found Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 146MB) Encoding state machine selected[2:0] (in view: work.arbiter2_32s_32s_32s_32s(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 @N: MF135 :"c:\tfg\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v":2664:0:2664:5|RAM registers_1[31:0] (in view: work.lm32_cpu(verilog)) is 32 words by 32 bits. @N: MF135 :"c:\tfg\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v":2664:0:2664:5|RAM registers[31:0] (in view: work.lm32_cpu(verilog)) is 32 words by 32 bits. @N: MF179 :"c:\tfg\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v":1490:18:1490:45|Found 5 by 5 bit equality operator ('==') un1_raw_w_1 (in view: work.lm32_cpu(verilog)) @N: MF179 :"c:\tfg\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v":1585:18:1585:44|Found 32 by 32 bit equality operator ('==') cmp_zero (in view: work.lm32_cpu(verilog)) @N: MF179 :"c:\tfg\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v":1485:18:1485:45|Found 5 by 5 bit equality operator ('==') un1_raw_x_0 (in view: work.lm32_cpu(verilog)) @N: MF179 :"c:\tfg\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v":1486:18:1486:45|Found 5 by 5 bit equality operator ('==') un1_raw_m_0 (in view: work.lm32_cpu(verilog)) @N: MF179 :"c:\tfg\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v":1487:18:1487:45|Found 5 by 5 bit equality operator ('==') un1_raw_w_0 (in view: work.lm32_cpu(verilog)) @N: MF179 :"c:\tfg\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v":1488:18:1488:45|Found 5 by 5 bit equality operator ('==') un1_raw_x_1 (in view: work.lm32_cpu(verilog)) @N: MF179 :"c:\tfg\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v":1489:18:1489:45|Found 5 by 5 bit equality operator ('==') un1_raw_m_1 (in view: work.lm32_cpu(verilog)) @W: BN132 :"c:\tfg\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v":2664:0:2664:5|Removing instance I1.lm32_inst.LM32.cpu.registersrff_12 because it is equivalent to instance I1.lm32_inst.LM32.cpu.registers_1rff_12. To keep the instance, apply constraint syn_preserve=1 on the instance. @W: BN132 :"c:\tfg\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v":2664:0:2664:5|Removing instance I1.lm32_inst.LM32.cpu.registersrff_13 because it is equivalent to instance I1.lm32_inst.LM32.cpu.registers_1rff_13. To keep the instance, apply constraint syn_preserve=1 on the instance. @W: BN132 :"c:\tfg\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v":2664:0:2664:5|Removing instance I1.lm32_inst.LM32.cpu.registersrff_14 because it is equivalent to instance I1.lm32_inst.LM32.cpu.registers_1rff_14. To keep the instance, apply constraint syn_preserve=1 on the instance. @W: BN132 :"c:\tfg\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v":2664:0:2664:5|Removing instance I1.lm32_inst.LM32.cpu.registersrff_15 because it is equivalent to instance I1.lm32_inst.LM32.cpu.registers_1rff_15. To keep the instance, apply constraint syn_preserve=1 on the instance. @W: BN132 :"c:\tfg\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v":2664:0:2664:5|Removing instance I1.lm32_inst.LM32.cpu.registersrff_16 because it is equivalent to instance I1.lm32_inst.LM32.cpu.registers_1rff_16. To keep the instance, apply constraint syn_preserve=1 on the instance. @W: BN132 :"c:\tfg\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v":2664:0:2664:5|Removing instance I1.lm32_inst.LM32.cpu.registersrff_17 because it is equivalent to instance I1.lm32_inst.LM32.cpu.registers_1rff_17. To keep the instance, apply constraint syn_preserve=1 on the instance. @W: BN132 :"c:\tfg\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v":2664:0:2664:5|Removing instance I1.lm32_inst.LM32.cpu.registersrff_18 because it is equivalent to instance I1.lm32_inst.LM32.cpu.registers_1rff_18. To keep the instance, apply constraint syn_preserve=1 on the instance. @W: BN132 :"c:\tfg\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v":2664:0:2664:5|Removing instance I1.lm32_inst.LM32.cpu.registersrff_19 because it is equivalent to instance I1.lm32_inst.LM32.cpu.registers_1rff_19. To keep the instance, apply constraint syn_preserve=1 on the instance. Encoding state machine state[3:0] (in view: work.lm32_icache_Z1_layer2(verilog)) original code -> new code 0001 -> 00 0010 -> 01 0100 -> 10 1000 -> 11 @N: MO225 :"c:\tfg\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_icache.v":403:0:403:5|There are no possible illegal states for state machine state[3:0] (in view: work.lm32_icache_Z1_layer2(verilog)); safe FSM implementation is not required. @N:"c:\tfg\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_icache.v":403:0:403:5|Found counter in view:work.lm32_icache_Z1_layer2(verilog) inst flush_set[6:0] @N: MF179 :"c:\tfg\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_ram.v":297:6:297:11|Found 7 by 7 bit equality operator ('==') adreg (in view: VhdlGenLib.proy_glob_RAM_R_W_128_19_TFFF_block_ram_ns_virtex2(netlist)) @N: MF179 :"c:\tfg\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_ram.v":297:6:297:11|Found 7 by 7 bit equality operator ('==') adreg (in view: VhdlGenLib.proy_glob_RAM_R_W_128_32_TFFF_block_ram_ns_virtex2(netlist)) @N: MF179 :"c:\tfg\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_icache.v":303:24:303:94|Found 19 by 19 bit equality operator ('==') way_match[0] (in view: work.lm32_icache_Z1_layer2(verilog)) @N: MF179 :"c:\tfg\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_load_store_unit.v":360:11:360:103|Found 30 by 30 bit equality operator ('==') un1_load_store_address_x_2 (in view: work.lm32_load_store_unit_1s_128s_4s_0_100663295_1s_2s_2s(verilog)) Encoding state machine state[2:0] (in view: work.lm32_dcache_Z3_layer2(verilog)) original code -> new code 001 -> 00 010 -> 01 100 -> 10 @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_dcache.v":464:0:464:5|Removing sequential instance refill_address[1] (in view: work.lm32_dcache_Z3_layer2(verilog)) because it does not drive other instances. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_dcache.v":464:0:464:5|Removing sequential instance refill_address[0] (in view: work.lm32_dcache_Z3_layer2(verilog)) because it does not drive other instances. @N:"c:\tfg\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_dcache.v":464:0:464:5|Found counter in view:work.lm32_dcache_Z3_layer2(verilog) inst flush_set[6:0] @N: MF179 :"c:\tfg\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_ram.v":297:6:297:11|Found 7 by 7 bit equality operator ('==') adreg (in view: VhdlGenLib.proy_glob_RAM_R_W_128_19_TFFF_block_ram_ns_virtex2_0(netlist)) @N: MF179 :"c:\tfg\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_ram.v":297:6:297:11|Found 7 by 7 bit equality operator ('==') adreg (in view: VhdlGenLib.proy_glob_RAM_R_W_128_32_TFFF_block_ram_ns_virtex2_0(netlist)) @N: MF179 :"c:\tfg\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_dcache.v":326:24:326:94|Found 19 by 19 bit equality operator ('==') way_match[0] (in view: work.lm32_dcache_Z3_layer2(verilog)) Encoding state machine state[2:0] (in view: work.lm32_monitor(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 Encoding state machine state[2:0] (in view: work.asram_core_32s_32s_23s_4s_1s_1s_1s_0_1_2(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 Encoding state machine main_sm[6:0] (in view: work.flash_core_32s_25s_7s_7s_1s_4s(verilog)) original code -> new code 000 -> 0000001 001 -> 0000010 010 -> 0000100 011 -> 0001000 100 -> 0010000 101 -> 0100000 110 -> 1000000 Starting factoring (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 154MB peak: 156MB) Finished factoring (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 174MB peak: 175MB) @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/parallel_flash/rtl/verilog\flash_core.v":146:3:146:8|Removing sequential instance I1.lm32_inst.flash.core_inst.sram_addr_bst[0] (in view: work.proy_glob(verilog)) because it does not drive other instances. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/parallel_flash/rtl/verilog\flash_core.v":146:3:146:8|Removing sequential instance I1.lm32_inst.flash.core_inst.sram_addr_bst[15] (in view: work.proy_glob(verilog)) because it does not drive other instances. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/parallel_flash/rtl/verilog\flash_core.v":146:3:146:8|Removing sequential instance I1.lm32_inst.flash.core_inst.sram_addr_bst[14] (in view: work.proy_glob(verilog)) because it does not drive other instances. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/parallel_flash/rtl/verilog\flash_core.v":146:3:146:8|Removing sequential instance I1.lm32_inst.flash.core_inst.sram_addr_bst[13] (in view: work.proy_glob(verilog)) because it does not drive other instances. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/parallel_flash/rtl/verilog\flash_core.v":146:3:146:8|Removing sequential instance I1.lm32_inst.flash.core_inst.sram_addr_bst[12] (in view: work.proy_glob(verilog)) because it does not drive other instances. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/parallel_flash/rtl/verilog\flash_core.v":146:3:146:8|Removing sequential instance I1.lm32_inst.flash.core_inst.sram_addr_bst[11] (in view: work.proy_glob(verilog)) because it does not drive other instances. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/parallel_flash/rtl/verilog\flash_core.v":146:3:146:8|Removing sequential instance I1.lm32_inst.flash.core_inst.sram_addr_bst[10] (in view: work.proy_glob(verilog)) because it does not drive other instances. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/parallel_flash/rtl/verilog\flash_core.v":146:3:146:8|Removing sequential instance I1.lm32_inst.flash.core_inst.sram_addr_bst[9] (in view: work.proy_glob(verilog)) because it does not drive other instances. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/parallel_flash/rtl/verilog\flash_core.v":146:3:146:8|Removing sequential instance I1.lm32_inst.flash.core_inst.sram_addr_bst[8] (in view: work.proy_glob(verilog)) because it does not drive other instances. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/parallel_flash/rtl/verilog\flash_core.v":146:3:146:8|Removing sequential instance I1.lm32_inst.flash.core_inst.sram_addr_bst[7] (in view: work.proy_glob(verilog)) because it does not drive other instances. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/parallel_flash/rtl/verilog\flash_core.v":146:3:146:8|Removing sequential instance I1.lm32_inst.flash.core_inst.sram_addr_bst[6] (in view: work.proy_glob(verilog)) because it does not drive other instances. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/parallel_flash/rtl/verilog\flash_core.v":146:3:146:8|Removing sequential instance I1.lm32_inst.flash.core_inst.sram_addr_bst[5] (in view: work.proy_glob(verilog)) because it does not drive other instances. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/parallel_flash/rtl/verilog\flash_core.v":146:3:146:8|Removing sequential instance I1.lm32_inst.flash.core_inst.sram_addr_bst[4] (in view: work.proy_glob(verilog)) because it does not drive other instances. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/parallel_flash/rtl/verilog\flash_core.v":146:3:146:8|Removing sequential instance I1.lm32_inst.flash.core_inst.sram_addr_bst[3] (in view: work.proy_glob(verilog)) because it does not drive other instances. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/parallel_flash/rtl/verilog\flash_core.v":146:3:146:8|Removing sequential instance I1.lm32_inst.flash.core_inst.sram_addr_bst[2] (in view: work.proy_glob(verilog)) because it does not drive other instances. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/parallel_flash/rtl/verilog\flash_core.v":146:3:146:8|Removing sequential instance I1.lm32_inst.flash.core_inst.sram_addr_bst[1] (in view: work.proy_glob(verilog)) because it does not drive other instances. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/parallel_flash/rtl/verilog\flash_core.v":146:3:146:8|Removing sequential instance I1.lm32_inst.flash.core_inst.sram_addr_bst[24] (in view: work.proy_glob(verilog)) because it does not drive other instances. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/parallel_flash/rtl/verilog\flash_core.v":146:3:146:8|Removing sequential instance I1.lm32_inst.flash.core_inst.sram_addr_bst[23] (in view: work.proy_glob(verilog)) because it does not drive other instances. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/parallel_flash/rtl/verilog\flash_core.v":146:3:146:8|Removing sequential instance I1.lm32_inst.flash.core_inst.sram_addr_bst[22] (in view: work.proy_glob(verilog)) because it does not drive other instances. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/parallel_flash/rtl/verilog\flash_core.v":146:3:146:8|Removing sequential instance I1.lm32_inst.flash.core_inst.sram_addr_bst[21] (in view: work.proy_glob(verilog)) because it does not drive other instances. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/parallel_flash/rtl/verilog\flash_core.v":146:3:146:8|Removing sequential instance I1.lm32_inst.flash.core_inst.sram_addr_bst[20] (in view: work.proy_glob(verilog)) because it does not drive other instances. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/parallel_flash/rtl/verilog\flash_core.v":146:3:146:8|Removing sequential instance I1.lm32_inst.flash.core_inst.sram_addr_bst[19] (in view: work.proy_glob(verilog)) because it does not drive other instances. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/parallel_flash/rtl/verilog\flash_core.v":146:3:146:8|Removing sequential instance I1.lm32_inst.flash.core_inst.sram_addr_bst[18] (in view: work.proy_glob(verilog)) because it does not drive other instances. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/parallel_flash/rtl/verilog\flash_core.v":146:3:146:8|Removing sequential instance I1.lm32_inst.flash.core_inst.sram_addr_bst[17] (in view: work.proy_glob(verilog)) because it does not drive other instances. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/parallel_flash/rtl/verilog\flash_core.v":146:3:146:8|Removing sequential instance I1.lm32_inst.flash.core_inst.sram_addr_bst[16] (in view: work.proy_glob(verilog)) because it does not drive other instances. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/parallel_flash/rtl/verilog\flash_core.v":146:3:146:8|Removing sequential instance I1.lm32_inst.flash.core_inst.rd_bst (in view: work.proy_glob(verilog)) because it does not drive other instances. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/parallel_flash/rtl/verilog\flash_core.v":146:3:146:8|Removing sequential instance I1.lm32_inst.flash.core_inst.we_bst (in view: work.proy_glob(verilog)) because it does not drive other instances. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/asram_top/rtl/verilog\asram_core.v":446:7:446:12|Removing sequential instance I1.lm32_inst.sram.core_inst.genblk2\.genblk1\.sram_be[3] (in view: work.proy_glob(verilog)) because it does not drive other instances. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/asram_top/rtl/verilog\asram_core.v":446:7:446:12|Removing sequential instance I1.lm32_inst.sram.core_inst.genblk2\.genblk1\.sram_be[2] (in view: work.proy_glob(verilog)) because it does not drive other instances. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/asram_top/rtl/verilog\asram_core.v":446:7:446:12|Removing sequential instance I1.lm32_inst.sram.core_inst.genblk2\.genblk1\.sram_be[1] (in view: work.proy_glob(verilog)) because it does not drive other instances. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/asram_top/rtl/verilog\asram_core.v":446:7:446:12|Removing sequential instance I1.lm32_inst.sram.core_inst.genblk2\.genblk1\.sram_be[0] (in view: work.proy_glob(verilog)) because it does not drive other instances. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/asram_top/rtl/verilog\asram_core.v":446:7:446:12|Removing sequential instance I1.lm32_inst.sram.core_inst.genblk2\.genblk1\.sram_addr[22] (in view: work.proy_glob(verilog)) because it does not drive other instances. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/asram_top/rtl/verilog\asram_core.v":446:7:446:12|Removing sequential instance I1.lm32_inst.sram.core_inst.genblk2\.genblk1\.sram_addr[21] (in view: work.proy_glob(verilog)) because it does not drive other instances. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/asram_top/rtl/verilog\asram_core.v":446:7:446:12|Removing sequential instance I1.lm32_inst.sram.core_inst.genblk2\.genblk1\.sram_addr[20] (in view: work.proy_glob(verilog)) because it does not drive other instances. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/asram_top/rtl/verilog\asram_core.v":446:7:446:12|Removing sequential instance I1.lm32_inst.sram.core_inst.genblk2\.genblk1\.sram_addr[19] (in view: work.proy_glob(verilog)) because it does not drive other instances. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/asram_top/rtl/verilog\asram_core.v":446:7:446:12|Removing sequential instance I1.lm32_inst.sram.core_inst.genblk2\.genblk1\.sram_addr[18] (in view: work.proy_glob(verilog)) because it does not drive other instances. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/asram_top/rtl/verilog\asram_core.v":446:7:446:12|Removing sequential instance I1.lm32_inst.sram.core_inst.genblk2\.genblk1\.sram_addr[17] (in view: work.proy_glob(verilog)) because it does not drive other instances. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/asram_top/rtl/verilog\asram_core.v":446:7:446:12|Removing sequential instance I1.lm32_inst.sram.core_inst.genblk2\.genblk1\.sram_addr[16] (in view: work.proy_glob(verilog)) because it does not drive other instances. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/asram_top/rtl/verilog\asram_core.v":446:7:446:12|Removing sequential instance I1.lm32_inst.sram.core_inst.genblk2\.genblk1\.sram_addr[15] (in view: work.proy_glob(verilog)) because it does not drive other instances. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/asram_top/rtl/verilog\asram_core.v":446:7:446:12|Removing sequential instance I1.lm32_inst.sram.core_inst.genblk2\.genblk1\.sram_addr[14] (in view: work.proy_glob(verilog)) because it does not drive other instances. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/asram_top/rtl/verilog\asram_core.v":446:7:446:12|Removing sequential instance I1.lm32_inst.sram.core_inst.genblk2\.genblk1\.sram_addr[13] (in view: work.proy_glob(verilog)) because it does not drive other instances. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/asram_top/rtl/verilog\asram_core.v":446:7:446:12|Removing sequential instance I1.lm32_inst.sram.core_inst.genblk2\.genblk1\.sram_addr[12] (in view: work.proy_glob(verilog)) because it does not drive other instances. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/asram_top/rtl/verilog\asram_core.v":446:7:446:12|Removing sequential instance I1.lm32_inst.sram.core_inst.genblk2\.genblk1\.sram_addr[11] (in view: work.proy_glob(verilog)) because it does not drive other instances. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/asram_top/rtl/verilog\asram_core.v":446:7:446:12|Removing sequential instance I1.lm32_inst.sram.core_inst.genblk2\.genblk1\.sram_addr[10] (in view: work.proy_glob(verilog)) because it does not drive other instances. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/asram_top/rtl/verilog\asram_core.v":446:7:446:12|Removing sequential instance I1.lm32_inst.sram.core_inst.genblk2\.genblk1\.sram_addr[9] (in view: work.proy_glob(verilog)) because it does not drive other instances. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/asram_top/rtl/verilog\asram_core.v":446:7:446:12|Removing sequential instance I1.lm32_inst.sram.core_inst.genblk2\.genblk1\.sram_addr[8] (in view: work.proy_glob(verilog)) because it does not drive other instances. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/asram_top/rtl/verilog\asram_core.v":446:7:446:12|Removing sequential instance I1.lm32_inst.sram.core_inst.genblk2\.genblk1\.sram_addr[7] (in view: work.proy_glob(verilog)) because it does not drive other instances. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/asram_top/rtl/verilog\asram_core.v":446:7:446:12|Removing sequential instance I1.lm32_inst.sram.core_inst.genblk2\.genblk1\.sram_addr[6] (in view: work.proy_glob(verilog)) because it does not drive other instances. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/asram_top/rtl/verilog\asram_core.v":446:7:446:12|Removing sequential instance I1.lm32_inst.sram.core_inst.genblk2\.genblk1\.sram_addr[5] (in view: work.proy_glob(verilog)) because it does not drive other instances. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/asram_top/rtl/verilog\asram_core.v":446:7:446:12|Removing sequential instance I1.lm32_inst.sram.core_inst.genblk2\.genblk1\.sram_addr[4] (in view: work.proy_glob(verilog)) because it does not drive other instances. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/asram_top/rtl/verilog\asram_core.v":446:7:446:12|Removing sequential instance I1.lm32_inst.sram.core_inst.genblk2\.genblk1\.sram_addr[3] (in view: work.proy_glob(verilog)) because it does not drive other instances. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/asram_top/rtl/verilog\asram_core.v":446:7:446:12|Removing sequential instance I1.lm32_inst.sram.core_inst.genblk2\.genblk1\.sram_addr[2] (in view: work.proy_glob(verilog)) because it does not drive other instances. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_load_store_unit.v":623:0:623:5|Removing sequential instance I1.lm32_inst.LM32.cpu.load_store_unit.d_adr_o[1] (in view: work.proy_glob(verilog)) because it does not drive other instances. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_load_store_unit.v":623:0:623:5|Removing sequential instance I1.lm32_inst.LM32.cpu.load_store_unit.d_adr_o[0] (in view: work.proy_glob(verilog)) because it does not drive other instances. Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 167MB peak: 178MB) Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 163MB peak: 178MB) @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/parallel_flash/rtl/verilog\flash_core.v":146:3:146:8|Removing sequential instance I1.lm32_inst.flash.core_inst.main_sm[4] (in view: work.proy_glob(verilog)) because it does not drive other instances. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/asram_top/rtl/verilog\asram_core.v":162:3:162:8|Removing sequential instance I1.lm32_inst.sram.core_inst.state[1] (in view: work.proy_glob(verilog)) because it does not drive other instances. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_interrupt.v":219:0:219:5|Removing sequential instance I1.lm32_inst.LM32.cpu.interrupt.genblk2\.ip[7] (in view: work.proy_glob(verilog)) because it does not drive other instances. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_interrupt.v":219:0:219:5|Removing sequential instance I1.lm32_inst.LM32.cpu.interrupt.genblk2\.ip[6] (in view: work.proy_glob(verilog)) because it does not drive other instances. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_interrupt.v":219:0:219:5|Removing sequential instance I1.lm32_inst.LM32.cpu.interrupt.genblk2\.ip[5] (in view: work.proy_glob(verilog)) because it does not drive other instances. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_interrupt.v":219:0:219:5|Removing sequential instance I1.lm32_inst.LM32.cpu.interrupt.genblk2\.ip[4] (in view: work.proy_glob(verilog)) because it does not drive other instances. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_interrupt.v":219:0:219:5|Removing sequential instance I1.lm32_inst.LM32.cpu.interrupt.genblk2\.ip[3] (in view: work.proy_glob(verilog)) because it does not drive other instances. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_interrupt.v":219:0:219:5|Removing sequential instance I1.lm32_inst.LM32.cpu.interrupt.genblk2\.ip[2] (in view: work.proy_glob(verilog)) because it does not drive other instances. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_interrupt.v":219:0:219:5|Removing sequential instance I1.lm32_inst.LM32.cpu.interrupt.genblk2\.ip[1] (in view: work.proy_glob(verilog)) because it does not drive other instances. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_interrupt.v":219:0:219:5|Removing sequential instance I1.lm32_inst.LM32.cpu.interrupt.genblk2\.ip[0] (in view: work.proy_glob(verilog)) because it does not drive other instances. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_interrupt.v":219:0:219:5|Removing sequential instance I1.lm32_inst.LM32.cpu.interrupt.genblk2\.ip[22] (in view: work.proy_glob(verilog)) because it does not drive other instances. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_interrupt.v":219:0:219:5|Removing sequential instance I1.lm32_inst.LM32.cpu.interrupt.genblk2\.ip[21] (in view: work.proy_glob(verilog)) because it does not drive other instances. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_interrupt.v":219:0:219:5|Removing sequential instance I1.lm32_inst.LM32.cpu.interrupt.genblk2\.ip[20] (in view: work.proy_glob(verilog)) because it does not drive other instances. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_interrupt.v":219:0:219:5|Removing sequential instance I1.lm32_inst.LM32.cpu.interrupt.genblk2\.ip[19] (in view: work.proy_glob(verilog)) because it does not drive other instances. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_interrupt.v":219:0:219:5|Removing sequential instance I1.lm32_inst.LM32.cpu.interrupt.genblk2\.ip[18] (in view: work.proy_glob(verilog)) because it does not drive other instances. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_interrupt.v":219:0:219:5|Removing sequential instance I1.lm32_inst.LM32.cpu.interrupt.genblk2\.ip[17] (in view: work.proy_glob(verilog)) because it does not drive other instances. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_interrupt.v":219:0:219:5|Removing sequential instance I1.lm32_inst.LM32.cpu.interrupt.genblk2\.ip[16] (in view: work.proy_glob(verilog)) because it does not drive other instances. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_interrupt.v":219:0:219:5|Removing sequential instance I1.lm32_inst.LM32.cpu.interrupt.genblk2\.ip[15] (in view: work.proy_glob(verilog)) because it does not drive other instances. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_interrupt.v":219:0:219:5|Removing sequential instance I1.lm32_inst.LM32.cpu.interrupt.genblk2\.ip[14] (in view: work.proy_glob(verilog)) because it does not drive other instances. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_interrupt.v":219:0:219:5|Removing sequential instance I1.lm32_inst.LM32.cpu.interrupt.genblk2\.ip[13] (in view: work.proy_glob(verilog)) because it does not drive other instances. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_interrupt.v":219:0:219:5|Removing sequential instance I1.lm32_inst.LM32.cpu.interrupt.genblk2\.ip[12] (in view: work.proy_glob(verilog)) because it does not drive other instances. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_interrupt.v":219:0:219:5|Removing sequential instance I1.lm32_inst.LM32.cpu.interrupt.genblk2\.ip[11] (in view: work.proy_glob(verilog)) because it does not drive other instances. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_interrupt.v":219:0:219:5|Removing sequential instance I1.lm32_inst.LM32.cpu.interrupt.genblk2\.ip[10] (in view: work.proy_glob(verilog)) because it does not drive other instances. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_interrupt.v":219:0:219:5|Removing sequential instance I1.lm32_inst.LM32.cpu.interrupt.genblk2\.ip[9] (in view: work.proy_glob(verilog)) because it does not drive other instances. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_interrupt.v":219:0:219:5|Removing sequential instance I1.lm32_inst.LM32.cpu.interrupt.genblk2\.ip[8] (in view: work.proy_glob(verilog)) because it does not drive other instances. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_interrupt.v":219:0:219:5|Removing sequential instance I1.lm32_inst.LM32.cpu.interrupt.genblk2\.ip[31] (in view: work.proy_glob(verilog)) because it does not drive other instances. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_interrupt.v":219:0:219:5|Removing sequential instance I1.lm32_inst.LM32.cpu.interrupt.genblk2\.ip[30] (in view: work.proy_glob(verilog)) because it does not drive other instances. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_interrupt.v":219:0:219:5|Removing sequential instance I1.lm32_inst.LM32.cpu.interrupt.genblk2\.ip[29] (in view: work.proy_glob(verilog)) because it does not drive other instances. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_interrupt.v":219:0:219:5|Removing sequential instance I1.lm32_inst.LM32.cpu.interrupt.genblk2\.ip[28] (in view: work.proy_glob(verilog)) because it does not drive other instances. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_interrupt.v":219:0:219:5|Removing sequential instance I1.lm32_inst.LM32.cpu.interrupt.genblk2\.ip[27] (in view: work.proy_glob(verilog)) because it does not drive other instances. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_interrupt.v":219:0:219:5|Removing sequential instance I1.lm32_inst.LM32.cpu.interrupt.genblk2\.ip[26] (in view: work.proy_glob(verilog)) because it does not drive other instances. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_interrupt.v":219:0:219:5|Removing sequential instance I1.lm32_inst.LM32.cpu.interrupt.genblk2\.ip[25] (in view: work.proy_glob(verilog)) because it does not drive other instances. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_interrupt.v":219:0:219:5|Removing sequential instance I1.lm32_inst.LM32.cpu.interrupt.genblk2\.ip[24] (in view: work.proy_glob(verilog)) because it does not drive other instances. @N: BN362 :"c:\tfg\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_interrupt.v":219:0:219:5|Removing sequential instance I1.lm32_inst.LM32.cpu.interrupt.genblk2\.ip[23] (in view: work.proy_glob(verilog)) because it does not drive other instances. Starting Early Timing Optimization (Real Time elapsed 0h:00m:11s; CPU Time elapsed 0h:00m:10s; Memory used current: 165MB peak: 178MB) Finished Early Timing Optimization (Real Time elapsed 0h:00m:11s; CPU Time elapsed 0h:00m:11s; Memory used current: 165MB peak: 178MB) Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:11s; CPU Time elapsed 0h:00m:11s; Memory used current: 164MB peak: 178MB) Finished preparing to map (Real Time elapsed 0h:00m:12s; CPU Time elapsed 0h:00m:12s; Memory used current: 164MB peak: 178MB) @N: FX1019 :"c:\tfg\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_jtag.v":292:3:292:8|Adding ASYNC_REG property on synchronizing instance I1.lm32_inst.LM32.cpu.jtag.rx_toggle_r (in view: work.proy_glob(verilog)). Finished technology mapping (Real Time elapsed 0h:00m:15s; CPU Time elapsed 0h:00m:14s; Memory used current: 177MB peak: 242MB) Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:15s 994.91ns 2326 / 1448 @N: FX1019 :"c:\tfg\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_jtag.v":292:3:292:8|Adding ASYNC_REG property on synchronizing instance I1.lm32_inst.LM32.cpu.jtag.rx_toggle_r (in view: work.proy_glob(verilog)). Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:16s; CPU Time elapsed 0h:00m:15s; Memory used current: 177MB peak: 242MB) @N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. @N: FO126 :"c:\tfg\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v":2664:0:2664:5|Generating RAM I1.lm32_inst.LM32.cpu.registers_1[31:0] @N: FO126 :"c:\tfg\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v":2664:0:2664:5|Generating RAM I1.lm32_inst.LM32.cpu.registers[31:0] Finished restoring hierarchy (Real Time elapsed 0h:00m:18s; CPU Time elapsed 0h:00m:17s; Memory used current: 180MB peak: 242MB) @S |Clock Optimization Summary #### START OF CLOCK OPTIMIZATION REPORT #####[ 2 non-gated/non-generated clock tree(s) driving 1482 clock pin(s) of sequential element(s) 2 gated/generated clock tree(s) driving 23 clock pin(s) of sequential element(s) 0 instances converted, 23 sequential instances remain driven by gated/generated clocks ========================================= Non-Gated/Non-Generated Clocks ========================================= Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance ------------------------------------------------------------------------------------------------------------------ @K:CKID0003 sal_osc port 1 I27.FF_0 @K:CKID0004 I27.FF_0 FD1P3DX 1481 I1.lm32_inst.LM32.debug_rom.write_data[31] ================================================================================================================== =========================================================================================================== Gated/Generated Clocks ============================================================================================================ Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance Explanation ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- @K:CKID0001 I1.lm32_inst.LM32.jtag_cores.jtagconn16_lm32_inst jtagconn16 22 I1.lm32_inst.LM32.jtag_cores.jtag_lm32_inst.ADDR_BIT2.DATA_OUT No gated clock conversion method for cell cell:LUCENT.FD1P3DX @K:CKID0002 I1.lm32_inst.LM32.jtag_cores.jtag_lm32_inst.REG_UPDATE ORCALUT4 1 I1.lm32_inst.LM32.cpu.jtag.rx_toggle No gated clock conversion method for cell cell:LUCENT.FD1S3DX =============================================================================================================================================================================================================================================== ##### END OF CLOCK OPTIMIZATION REPORT ######] Start Writing Netlists (Real Time elapsed 0h:00m:19s; CPU Time elapsed 0h:00m:18s; Memory used current: 136MB peak: 242MB) Writing Analyst data base C:\TFG\exp7\proy_glob\synwork\proy_glob_proy_glob_m.srm Finished Writing Netlist Databases (Real Time elapsed 0h:00m:20s; CPU Time elapsed 0h:00m:19s; Memory used current: 175MB peak: 242MB) Writing EDIF Netlist and constraint files @N: FX1056 |Writing EDF file: C:\TFG\exp7\proy_glob\proy_glob_proy_glob.edi L-2016.03L-1 @N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:21s; CPU Time elapsed 0h:00m:20s; Memory used current: 181MB peak: 242MB) Start final timing analysis (Real Time elapsed 0h:00m:21s; CPU Time elapsed 0h:00m:20s; Memory used current: 179MB peak: 242MB) @W: MT246 :"c:\tfg\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_addsub.v":102:7:102:12|Blackbox pmi_addsub_32s_32s_off_MachXO2_pmi_addsub is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W: MT246 :"c:\tfg\exp7\mic32\soc\../components/lm32_top/rtl/verilog\lm32_load_store_unit.v":318:7:318:9|Blackbox pmi_ram_dp_true_Z2_layer2 is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W: MT246 :"c:\tfg\exp7\mic32\soc\../components/lm32_top/rtl/verilog\jtag_cores.v":126:70:126:89|Blackbox jtagconn16 is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W: MT420 |Found inferred clock proy_glob|sal_osc with period 1000.00ns. Please declare a user-defined clock on object "p:sal_osc" @N: MT615 |Found clock div2|tdataout0_derived_clock with period 1000.00ns @W: MT420 |Found inferred clock jtag_cores|jtck with period 1000.00ns. Please declare a user-defined clock on object "n:I1.lm32_inst.LM32.jtag_cores.jtck" @W: MT420 |Found inferred clock jtag_lm32|REG_UPDATE_inferred_clock with period 1000.00ns. Please declare a user-defined clock on object "n:I1.lm32_inst.LM32.jtag_cores.jtag_lm32_inst.REG_UPDATE" ##### START OF TIMING REPORT #####[ # Timing Report written on Wed Sep 20 02:07:18 2017 # Top view: proy_glob Requested Frequency: 1.0 MHz Wire load mode: top Paths requested: 5 Constraint File(s): @N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing. @N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock. Performance Summary ******************* Worst slack in design: 993.620 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group --------------------------------------------------------------------------------------------------------------------------------------------------------------------- div2|tdataout0_derived_clock 1.0 MHz 123.8 MHz 1000.000 8.080 1983.840 derived (from proy_glob|sal_osc) Inferred_clkgroup_0 jtag_cores|jtck 1.0 MHz 636.2 MHz 1000.000 1.572 998.428 inferred Inferred_clkgroup_1 jtag_lm32|REG_UPDATE_inferred_clock 1.0 MHz 582.3 MHz 1000.000 1.717 998.283 inferred Inferred_clkgroup_2 proy_glob|sal_osc 1.0 MHz NA 1000.000 NA DCM/PLL inferred Inferred_clkgroup_0 System 1.0 MHz 459.2 MHz 1000.000 2.178 997.822 system system_clkgroup ===================================================================================================================================================================== @N: MT582 |Estimated period and frequency not reported for given clock unless the clock has at least one timing path which is not a false or a max delay path and that does not have excessive slack Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise ------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ------------------------------------------------------------------------------------------------------------------------------------------------------------------------- System System | 1000.000 997.822 | No paths - | No paths - | No paths - System jtag_cores|jtck | No paths - | No paths - | 1000.000 999.080 | No paths - System div2|tdataout0_derived_clock | 1000.000 993.620 | No paths - | No paths - | No paths - jtag_cores|jtck System | No paths - | No paths - | No paths - | 1000.000 998.956 jtag_cores|jtck jtag_cores|jtck | No paths - | 1000.000 998.428 | No paths - | No paths - jtag_cores|jtck div2|tdataout0_derived_clock | No paths - | No paths - | No paths - | Diff grp - div2|tdataout0_derived_clock System | 1000.000 995.622 | No paths - | No paths - | No paths - div2|tdataout0_derived_clock jtag_cores|jtck | No paths - | No paths - | Diff grp - | No paths - div2|tdataout0_derived_clock div2|tdataout0_derived_clock | 1000.000 1983.840 | No paths - | No paths - | No paths - jtag_lm32|REG_UPDATE_inferred_clock div2|tdataout0_derived_clock | No paths - | No paths - | No paths - | Diff grp - jtag_lm32|REG_UPDATE_inferred_clock jtag_lm32|REG_UPDATE_inferred_clock | No paths - | 1000.000 998.283 | No paths - | No paths - ========================================================================================================================================================================= Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: div2|tdataout0_derived_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------------------------ I1.lm32_inst.LM32.cpu.exception_m div2|tdataout0_derived_clock FD1P3DX Q exception_m 1.344 995.622 I1.lm32_inst.LM32.cpu.instruction_unit.icache.state[1] div2|tdataout0_derived_clock FD1S3DX Q state[1] 1.299 995.667 I1.lm32_inst.LM32.cpu.instruction_unit.icache.state[0] div2|tdataout0_derived_clock FD1S3DX Q state[0] 1.256 995.710 I1.lm32_inst.LM32.cpu.load_store_unit.dcache.state[0] div2|tdataout0_derived_clock FD1S3DX Q state[0] 1.252 995.714 I1.lm32_inst.LM32.cpu.instruction_unit.i_cyc_o div2|tdataout0_derived_clock FD1S3DX Q LM32I_STB_O 1.244 995.722 I1.lm32_inst.LM32.cpu.branch_m div2|tdataout0_derived_clock FD1P3DX Q branch_m 1.108 995.858 I1.lm32_inst.LM32.cpu.load_store_unit.stall_wb_load div2|tdataout0_derived_clock FD1P3DX Q stall_wb_load 0.972 995.994 I1.lm32_inst.LM32.cpu.load_x div2|tdataout0_derived_clock FD1P3DX Q load_x 1.228 996.306 I1.lm32_inst.LM32.cpu.load_store_unit.dcache.refill_request div2|tdataout0_derived_clock FD1P3DX Q dcache_refill_request 1.427 996.307 I1.lm32_inst.LM32.cpu.load_m div2|tdataout0_derived_clock FD1P3DX Q load_m 1.148 996.386 ================================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------- I1.lm32_inst.LM32.cpu.load_store_unit.ram div2|tdataout0_derived_clock pmi_ram_dp_true_Z2_layer2 ClockEnA stall_m_i_0_a2 1000.000 995.622 I1.lm32_inst.LM32.cpu.load_store_unit.ram div2|tdataout0_derived_clock pmi_ram_dp_true_Z2_layer2 ClockEnB stall_m_i_0_a2 1000.000 995.622 I1.lm32_inst.LM32.cpu.load_store_unit.ram div2|tdataout0_derived_clock pmi_ram_dp_true_Z2_layer2 WrB un1_store_q_m 1000.000 996.307 I1.lm32_inst.LM32.cpu.load_store_unit.ram div2|tdataout0_derived_clock pmi_ram_dp_true_Z2_layer2 DataInB[0] un4_dram_store_data_m[0] 1000.000 996.494 I1.lm32_inst.LM32.cpu.load_store_unit.ram div2|tdataout0_derived_clock pmi_ram_dp_true_Z2_layer2 DataInB[1] un4_dram_store_data_m[1] 1000.000 996.494 I1.lm32_inst.LM32.cpu.load_store_unit.ram div2|tdataout0_derived_clock pmi_ram_dp_true_Z2_layer2 DataInB[2] un4_dram_store_data_m[2] 1000.000 996.494 I1.lm32_inst.LM32.cpu.load_store_unit.ram div2|tdataout0_derived_clock pmi_ram_dp_true_Z2_layer2 DataInB[3] un4_dram_store_data_m[3] 1000.000 996.494 I1.lm32_inst.LM32.cpu.load_store_unit.ram div2|tdataout0_derived_clock pmi_ram_dp_true_Z2_layer2 DataInB[4] un4_dram_store_data_m[4] 1000.000 996.494 I1.lm32_inst.LM32.cpu.load_store_unit.ram div2|tdataout0_derived_clock pmi_ram_dp_true_Z2_layer2 DataInB[5] un4_dram_store_data_m[5] 1000.000 996.494 I1.lm32_inst.LM32.cpu.load_store_unit.ram div2|tdataout0_derived_clock pmi_ram_dp_true_Z2_layer2 DataInB[6] un4_dram_store_data_m[6] 1000.000 996.494 ============================================================================================================================================================================= Worst Path Information *********************** Path information for path number 1: Requested Period: 1000.000 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) + Estimated clock delay at ending point: 0.000 = Required time: 1000.000 - Propagation time: 4.378 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 995.622 Number of logic level(s): 2 Starting point: I1.lm32_inst.LM32.cpu.exception_m / Q Ending point: I1.lm32_inst.LM32.cpu.load_store_unit.ram / ClockEnA The start point is clocked by div2|tdataout0_derived_clock [rising] on pin CK The end point is clocked by System [rising] Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------------------ I1.lm32_inst.LM32.cpu.exception_m FD1P3DX Q Out 1.344 1.344 - exception_m Net - - - - 44 I1.lm32_inst.LM32.cpu.decoder.stall_m_i_0_o2 ORCALUT4 B In 0.000 1.344 - I1.lm32_inst.LM32.cpu.decoder.stall_m_i_0_o2 ORCALUT4 Z Out 1.017 2.361 - N_60 Net - - - - 1 I1.lm32_inst.LM32.cpu.decoder.stall_m_i_0_a2 ORCALUT4 A In 0.000 2.361 - I1.lm32_inst.LM32.cpu.decoder.stall_m_i_0_a2 ORCALUT4 Z Out 2.018 4.378 - stall_m_i_0_a2 Net - - - - 437 I1.lm32_inst.LM32.cpu.load_store_unit.ram pmi_ram_dp_true_Z2_layer2 ClockEnA In 0.000 4.378 - ==================================================================================================================================== ==================================== Detailed Report for Clock: jtag_cores|jtck ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------ I1.lm32_inst.LM32.jtag_cores.jtag_lm32_inst.ADDR_BIT1.tdoInt jtag_cores|jtck FD1P3DX Q tdibus[9] 1.044 998.428 I1.lm32_inst.LM32.jtag_cores.jtag_lm32_inst.ADDR_BIT0.tdoInt jtag_cores|jtck FD1P3DX Q tdibus[8] 1.044 998.428 I1.lm32_inst.LM32.jtag_cores.jtag_lm32_inst.DATA_BIT7.tdoInt jtag_cores|jtck FD1P3DX Q tdibus[7] 1.044 998.428 I1.lm32_inst.LM32.jtag_cores.jtag_lm32_inst.DATA_BIT6.tdoInt jtag_cores|jtck FD1P3DX Q tdibus[6] 1.044 998.428 I1.lm32_inst.LM32.jtag_cores.jtag_lm32_inst.DATA_BIT5.tdoInt jtag_cores|jtck FD1P3DX Q tdibus[5] 1.044 998.428 I1.lm32_inst.LM32.jtag_cores.jtag_lm32_inst.DATA_BIT4.tdoInt jtag_cores|jtck FD1P3DX Q tdibus[4] 1.044 998.428 I1.lm32_inst.LM32.jtag_cores.jtag_lm32_inst.DATA_BIT3.tdoInt jtag_cores|jtck FD1P3DX Q tdibus[3] 1.044 998.428 I1.lm32_inst.LM32.jtag_cores.jtag_lm32_inst.DATA_BIT2.tdoInt jtag_cores|jtck FD1P3DX Q tdibus[2] 1.044 998.428 I1.lm32_inst.LM32.jtag_cores.jtag_lm32_inst.DATA_BIT1.tdoInt jtag_cores|jtck FD1P3DX Q tdibus[1] 1.044 998.428 I1.lm32_inst.LM32.jtag_cores.jtag_lm32_inst.DATA_BIT0.tdoInt jtag_cores|jtck FD1P3DX Q tdibus[0] 1.044 998.428 ========================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ---------------------------------------------------------------------------------------------------------------------------------------------- I1.lm32_inst.LM32.jtag_cores.jtag_lm32_inst.ADDR_BIT2.tdoInt jtag_cores|jtck FD1P3DX D N_45_i 1000.089 998.428 I1.lm32_inst.LM32.jtag_cores.jtag_lm32_inst.ADDR_BIT1.tdoInt jtag_cores|jtck FD1P3DX D tdoInt_RNO_8 1000.089 998.428 I1.lm32_inst.LM32.jtag_cores.jtag_lm32_inst.ADDR_BIT0.tdoInt jtag_cores|jtck FD1P3DX D tdoInt_RNO_7 1000.089 998.428 I1.lm32_inst.LM32.jtag_cores.jtag_lm32_inst.DATA_BIT7.tdoInt jtag_cores|jtck FD1P3DX D tdoInt_RNO_6 1000.089 998.428 I1.lm32_inst.LM32.jtag_cores.jtag_lm32_inst.DATA_BIT6.tdoInt jtag_cores|jtck FD1P3DX D tdoInt_RNO_5 1000.089 998.428 I1.lm32_inst.LM32.jtag_cores.jtag_lm32_inst.DATA_BIT5.tdoInt jtag_cores|jtck FD1P3DX D tdoInt_RNO_4 1000.089 998.428 I1.lm32_inst.LM32.jtag_cores.jtag_lm32_inst.DATA_BIT4.tdoInt jtag_cores|jtck FD1P3DX D tdoInt_RNO_3 1000.089 998.428 I1.lm32_inst.LM32.jtag_cores.jtag_lm32_inst.DATA_BIT3.tdoInt jtag_cores|jtck FD1P3DX D tdoInt_RNO_2 1000.089 998.428 I1.lm32_inst.LM32.jtag_cores.jtag_lm32_inst.DATA_BIT2.tdoInt jtag_cores|jtck FD1P3DX D tdoInt_RNO_1 1000.089 998.428 I1.lm32_inst.LM32.jtag_cores.jtag_lm32_inst.DATA_BIT1.tdoInt jtag_cores|jtck FD1P3DX D tdoInt_RNO_0 1000.089 998.428 ============================================================================================================================================== Worst Path Information *********************** Path information for path number 1: Requested Period: 1000.000 - Setup time: -0.089 + Clock delay at ending point: 0.000 (ideal) = Required time: 1000.089 - Propagation time: 1.661 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 998.428 Number of logic level(s): 1 Starting point: I1.lm32_inst.LM32.jtag_cores.jtag_lm32_inst.ADDR_BIT1.tdoInt / Q Ending point: I1.lm32_inst.LM32.jtag_cores.jtag_lm32_inst.ADDR_BIT2.tdoInt / D The start point is clocked by jtag_cores|jtck [falling] on pin CK The end point is clocked by jtag_cores|jtck [falling] on pin CK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------------------------------------------- I1.lm32_inst.LM32.jtag_cores.jtag_lm32_inst.ADDR_BIT1.tdoInt FD1P3DX Q Out 1.044 1.044 - tdibus[9] Net - - - - 2 I1.lm32_inst.LM32.jtag_cores.jtag_lm32_inst.ADDR_BIT2.tdoInt_RNO ORCALUT4 B In 0.000 1.044 - I1.lm32_inst.LM32.jtag_cores.jtag_lm32_inst.ADDR_BIT2.tdoInt_RNO ORCALUT4 Z Out 0.617 1.661 - N_45_i Net - - - - 1 I1.lm32_inst.LM32.jtag_cores.jtag_lm32_inst.ADDR_BIT2.tdoInt FD1P3DX D In 0.000 1.661 - =================================================================================================================================== ==================================== Detailed Report for Clock: jtag_lm32|REG_UPDATE_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------------------------------------- I1.lm32_inst.LM32.cpu.jtag.rx_toggle jtag_lm32|REG_UPDATE_inferred_clock FD1S3DX Q rx_toggle 1.044 998.283 ====================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------------------------------- I1.lm32_inst.LM32.cpu.jtag.rx_toggle jtag_lm32|REG_UPDATE_inferred_clock FD1S3DX D rx_toggle_i 999.894 998.283 ========================================================================================================================================= Worst Path Information *********************** Path information for path number 1: Requested Period: 1000.000 - Setup time: 0.106 + Clock delay at ending point: 0.000 (ideal) = Required time: 999.894 - Propagation time: 1.612 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 998.283 Number of logic level(s): 1 Starting point: I1.lm32_inst.LM32.cpu.jtag.rx_toggle / Q Ending point: I1.lm32_inst.LM32.cpu.jtag.rx_toggle / D The start point is clocked by jtag_lm32|REG_UPDATE_inferred_clock [falling] on pin CK The end point is clocked by jtag_lm32|REG_UPDATE_inferred_clock [falling] on pin CK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------------- I1.lm32_inst.LM32.cpu.jtag.rx_toggle FD1S3DX Q Out 1.044 1.044 - rx_toggle Net - - - - 2 I1.lm32_inst.LM32.cpu.jtag.rx_toggle_RNO INV A In 0.000 1.044 - I1.lm32_inst.LM32.cpu.jtag.rx_toggle_RNO INV Z Out 0.568 1.612 - rx_toggle_i Net - - - - 1 I1.lm32_inst.LM32.cpu.jtag.rx_toggle FD1S3DX D In 0.000 1.612 - ========================================================================================================== ==================================== Detailed Report for Clock: System ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- I1.lm32_inst.LM32.cpu.adder.addsub.genblk1\.addsub System pmi_addsub_32s_32s_off_MachXO2_pmi_addsub Result[19] adder_result_x[19] 0.000 993.620 I1.lm32_inst.LM32.cpu.adder.addsub.genblk1\.addsub System pmi_addsub_32s_32s_off_MachXO2_pmi_addsub Result[20] adder_result_x[20] 0.000 993.620 I1.lm32_inst.LM32.cpu.adder.addsub.genblk1\.addsub System pmi_addsub_32s_32s_off_MachXO2_pmi_addsub Result[21] adder_result_x[21] 0.000 993.620 I1.lm32_inst.LM32.cpu.adder.addsub.genblk1\.addsub System pmi_addsub_32s_32s_off_MachXO2_pmi_addsub Result[22] adder_result_x[22] 0.000 993.620 I1.lm32_inst.LM32.cpu.adder.addsub.genblk1\.addsub System pmi_addsub_32s_32s_off_MachXO2_pmi_addsub Result[25] adder_result_x[25] 0.000 994.564 I1.lm32_inst.LM32.cpu.adder.addsub.genblk1\.addsub System pmi_addsub_32s_32s_off_MachXO2_pmi_addsub Result[26] adder_result_x[26] 0.000 994.564 I1.lm32_inst.LM32.cpu.adder.addsub.genblk1\.addsub System pmi_addsub_32s_32s_off_MachXO2_pmi_addsub Result[11] adder_result_x[11] 0.000 994.636 I1.lm32_inst.LM32.cpu.adder.addsub.genblk1\.addsub System pmi_addsub_32s_32s_off_MachXO2_pmi_addsub Result[12] adder_result_x[12] 0.000 994.636 I1.lm32_inst.LM32.cpu.adder.addsub.genblk1\.addsub System pmi_addsub_32s_32s_off_MachXO2_pmi_addsub Result[13] adder_result_x[13] 0.000 994.636 I1.lm32_inst.LM32.cpu.adder.addsub.genblk1\.addsub System pmi_addsub_32s_32s_off_MachXO2_pmi_addsub Result[14] adder_result_x[14] 0.000 994.636 ============================================================================================================================================================================ Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ---------------------------------------------------------------------------------------------------------------------------------------------- I1.lm32_inst.LM32.cpu.load_store_unit.stall_wb_load System FD1P3DX SP stall_wb_load_1_sqmuxa_1_i 999.528 993.620 I1.lm32_inst.LM32.cpu.load_store_unit.stall_wb_load System FD1P3DX D stall_wb_load9 999.894 994.602 I1.lm32_inst.LM32.cpu.operand_1_x[17] System FD1P3DX D d_result_1[17] 999.894 994.742 I1.lm32_inst.LM32.cpu.operand_1_x[27] System FD1P3DX D d_result_1[27] 999.894 994.742 I1.lm32_inst.LM32.cpu.load_store_unit.dram_bypass_en System FD1P3DX SP un1_dram_bypass_en5 999.528 994.746 I1.lm32_inst.LM32.cpu.load_store_unit.dram_select_m System FD1P3DX D dram_select_x 1000.089 995.269 I1.lm32_inst.LM32.cpu.load_store_unit.dram_bypass_en System FD1P3DX D N_697_i 1000.089 995.307 I1.lm32_inst.LM32.cpu.load_store_unit.wb_select_m System FD1P3DX D un6_dram_select_x 999.894 995.691 I1.lm32_inst.LM32.cpu.branch_target_x[7] System FD1P3DX D branch_target_x_2[7] 999.894 995.759 I1.lm32_inst.LM32.cpu.branch_target_x[11] System FD1P3DX D branch_target_x_2[11] 999.894 995.759 ============================================================================================================================================== Worst Path Information *********************** Path information for path number 1: Requested Period: 1000.000 - Setup time: 0.472 + Clock delay at ending point: 0.000 (ideal) = Required time: 999.528 - Propagation time: 5.909 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (critical) : 993.620 Number of logic level(s): 6 Starting point: I1.lm32_inst.LM32.cpu.adder.addsub.genblk1\.addsub / Result[19] Ending point: I1.lm32_inst.LM32.cpu.load_store_unit.stall_wb_load / SP The start point is clocked by System [rising] The end point is clocked by div2|tdataout0_derived_clock [rising] on pin CK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- I1.lm32_inst.LM32.cpu.adder.addsub.genblk1\.addsub pmi_addsub_32s_32s_off_MachXO2_pmi_addsub Result[19] Out 0.000 0.000 - adder_result_x[19] Net - - - - 3 I1.lm32_inst.LM32.cpu.load_store_unit.un6_dram_select_xlto24_7 ORCALUT4 A In 0.000 0.000 - I1.lm32_inst.LM32.cpu.load_store_unit.un6_dram_select_xlto24_7 ORCALUT4 Z Out 1.017 1.017 - un6_dram_select_xlto24_7 Net - - - - 1 I1.lm32_inst.LM32.cpu.load_store_unit.un6_dram_select_xlto24_10 ORCALUT4 C In 0.000 1.017 - I1.lm32_inst.LM32.cpu.load_store_unit.un6_dram_select_xlto24_10 ORCALUT4 Z Out 1.017 2.034 - un6_dram_select_xlto24_10 Net - - - - 1 I1.lm32_inst.LM32.cpu.load_store_unit.un6_dram_select_xlto26 ORCALUT4 D In 0.000 2.034 - I1.lm32_inst.LM32.cpu.load_store_unit.un6_dram_select_xlto26 ORCALUT4 Z Out 1.017 3.050 - un6_dram_select_xlt31 Net - - - - 1 I1.lm32_inst.LM32.cpu.load_store_unit.un6_dram_select_xlto31 ORCALUT4 D In 0.000 3.050 - I1.lm32_inst.LM32.cpu.load_store_unit.un6_dram_select_xlto31 ORCALUT4 Z Out 1.153 4.203 - un6_dram_select_x Net - - - - 3 I1.lm32_inst.LM32.cpu.load_store_unit.stall_wb_load9 ORCALUT4 B In 0.000 4.203 - I1.lm32_inst.LM32.cpu.load_store_unit.stall_wb_load9 ORCALUT4 Z Out 1.089 5.292 - stall_wb_load9 Net - - - - 2 I1.lm32_inst.LM32.cpu.load_store_unit.stall_wb_load_1_sqmuxa_1_i ORCALUT4 C In 0.000 5.292 - I1.lm32_inst.LM32.cpu.load_store_unit.stall_wb_load_1_sqmuxa_1_i ORCALUT4 Z Out 0.617 5.909 - stall_wb_load_1_sqmuxa_1_i Net - - - - 1 I1.lm32_inst.LM32.cpu.load_store_unit.stall_wb_load FD1P3DX SP In 0.000 5.909 - ========================================================================================================================================================================== ##### END OF TIMING REPORT #####] Constraints that could not be applied None Finished final timing analysis (Real Time elapsed 0h:00m:21s; CPU Time elapsed 0h:00m:21s; Memory used current: 179MB peak: 242MB) Finished timing report (Real Time elapsed 0h:00m:21s; CPU Time elapsed 0h:00m:21s; Memory used current: 179MB peak: 242MB) --------------------------------------- Resource Usage Report Part: lcmxo2_7000he-4 Register bits: 1449 of 6864 (21%) PIC Latch: 0 I/O cells: 44 Block Rams : 12 of 26 (46%) Details: BB: 32 CCU2D: 76 CU2: 1 DP8KC: 4 DPR16X4C: 32 FADD2B: 1 FD1P3AX: 32 FD1P3BX: 45 FD1P3DX: 999 FD1S3AX: 148 FD1S3BX: 7 FD1S3DX: 210 GSR: 1 IB: 2 INV: 9 OB: 10 OFS1P3DX: 8 ORCALUT4: 2397 PDPW8KC: 8 PFUMX: 249 PUR: 1 VHI: 34 VLO: 36 false: 7 true: 9 Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:22s; CPU Time elapsed 0h:00m:21s; Memory used current: 41MB peak: 242MB) Process took 0h:00m:22s realtime, 0h:00m:21s cputime # Wed Sep 20 02:07:18 2017 ###########################################################]