Synthesis Report
#Build: Synplify Pro L-2016.03L-1, Build 097R, Jul  4 2016
#install: C:\lscc\diamond\3.8\synpbase
#OS: Windows 8 6.2
#Hostname: RORDRIGO

# Tue Sep 05 22:00:50 2017

#Implementation: control_disp

Synopsys HDL Compiler, version comp2016q2rc, Build 192R, built Jul  5 2016
@N|Running in 64-bit mode
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.

Synopsys VHDL Compiler, version comp2016q2rc, Build 192R, built Jul  5 2016
@N|Running in 64-bit mode
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.

@N: CD720 :"C:\lscc\diamond\3.8\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns
@N:"C:\TFG\exp1\control_disp.vhd":5:7:5:18|Top entity is set to control_disp.
File C:\TFG\exp1\control_disp.vhd changed - recompiling
VHDL syntax check successful!
File C:\TFG\exp1\control_disp.vhd changed - recompiling
@N: CD630 :"C:\TFG\exp1\control_disp.vhd":5:7:5:18|Synthesizing work.control_disp.control_arch.
Post processing for work.control_disp.control_arch
@W: CL240 :"C:\TFG\exp1\control_disp.vhd":10:2:10:6|sal32 is not assigned a value (floating) -- simulation mismatch possible. 

At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 70MB peak: 71MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Tue Sep 05 22:00:51 2017

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Synopsys Netlist Linker, version comp2016q2rc, Build 192R, built Jul  5 2016
@N|Running in 64-bit mode
File C:\TFG\exp1\control_disp\synwork\layer0.srs changed - recompiling

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Tue Sep 05 22:00:51 2017

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@END

At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Tue Sep 05 22:00:51 2017

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Synopsys Netlist Linker, version comp2016q2rc, Build 192R, built Jul  5 2016
@N|Running in 64-bit mode
File C:\TFG\exp1\control_disp\synwork\control_disp_control_disp_comp.srs changed - recompiling

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Tue Sep 05 22:00:52 2017

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Pre-mapping Report

Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1498R, Built Jul  5 2016 10:30:31
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
Product Version L-2016.03L-1

Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)

@A: MF827 |No constraint file specified.
@L: C:\TFG\exp1\control_disp\control_disp_control_disp_scck.rpt 
Printing clock  summary report in "C:\TFG\exp1\control_disp\control_disp_control_disp_scck.rpt" file 
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 112MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 114MB)

ICG Latch Removal Summary:
Number of ICG latches removed:	0
Number of ICG latches not removed:	0
syn_allowed_resources : blockrams=7  set on top level netlist control_disp

Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 141MB)



Clock Summary
*****************

Start                Requested     Requested     Clock        Clock                   Clock
Clock                Frequency     Period        Type         Group                   Load 
-------------------------------------------------------------------------------------------
control_disp|clk     1.0 MHz       1000.000      inferred     Inferred_clkgroup_0     21   
===========================================================================================

@W: MT529 :"c:\tfg\exp1\control_disp.vhd":22:8:22:9|Found inferred clock control_disp|clk which controls 21 sequential elements including cnt[20:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 

Finished Pre Mapping Phase.

Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)

None
None

Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)

Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 141MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Tue Sep 05 22:00:53 2017

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Map & Optimize Report

Synopsys Lattice Technology Mapper, Version maplat, Build 1498R, Built Jul  5 2016 10:30:31
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
Product Version L-2016.03L-1

Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)

@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 111MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 114MB)



Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)


Available hyper_sources - for debug and ip models
	None Found


Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)


Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)


Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)


Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)


Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)


Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 141MB)


Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 141MB)


Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)


Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 141MB)


Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:00s		   994.55ns		  19 /        21

Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)

@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  

Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)



@S |Clock Optimization Summary


#### START OF CLOCK OPTIMIZATION REPORT #####[

1 non-gated/non-generated clock tree(s) driving 21 clock pin(s) of sequential element(s)
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
0 instances converted, 0 sequential instances remain driven by gated/generated clocks

=========================== Non-Gated/Non-Generated Clocks ============================
Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
---------------------------------------------------------------------------------------
@K:CKID0001       clk                 port                   21         cnt[0]         
=======================================================================================


##### END OF CLOCK OPTIMIZATION REPORT ######]


Start Writing Netlists (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 107MB peak: 141MB)

Writing Analyst data base C:\TFG\exp1\control_disp\synwork\control_disp_control_disp_m.srm

Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)

Writing EDIF Netlist and constraint files
@N: FX1056 |Writing EDF file: C:\TFG\exp1\control_disp\control_disp_control_disp.edi
L-2016.03L-1
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF 

Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 144MB)


Start final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 144MB)

@W: MT420 |Found inferred clock control_disp|clk with period 1000.00ns. Please declare a user-defined clock on object "p:clk"


##### START OF TIMING REPORT #####[
# Timing Report written on Tue Sep 05 22:00:54 2017
#


Top view:               control_disp
Requested Frequency:    1.0 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    
@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.

@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.



Performance Summary
*******************


Worst slack in design: 993.986

                     Requested     Estimated     Requested     Estimated                 Clock        Clock              
Starting Clock       Frequency     Frequency     Period        Period        Slack       Type         Group              
-------------------------------------------------------------------------------------------------------------------------
control_disp|clk     1.0 MHz       166.3 MHz     1000.000      6.015         993.986     inferred     Inferred_clkgroup_0
=========================================================================================================================





Clock Relationships
*******************

Clocks                              |    rise  to  rise     |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
----------------------------------------------------------------------------------------------------------------------------
Starting          Ending            |  constraint  slack    |  constraint  slack  |  constraint  slack  |  constraint  slack
----------------------------------------------------------------------------------------------------------------------------
control_disp|clk  control_disp|clk  |  1000.000    993.986  |  No paths    -      |  No paths    -      |  No paths    -    
============================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

No IO constraint found



====================================
Detailed Report for Clock: control_disp|clk
====================================



Starting Points with Worst Slack
********************************

             Starting                                            Arrival            
Instance     Reference            Type        Pin     Net        Time        Slack  
             Clock                                                                  
------------------------------------------------------------------------------------
cnt[0]       control_disp|clk     FD1S3DX     Q       cnt[0]     1.108       993.986
cnt[1]       control_disp|clk     FD1S3DX     Q       cnt[1]     1.044       994.192
cnt[2]       control_disp|clk     FD1S3DX     Q       cnt[2]     1.044       994.192
cnt[3]       control_disp|clk     FD1S3DX     Q       cnt[3]     1.044       994.335
cnt[4]       control_disp|clk     FD1S3DX     Q       cnt[4]     1.044       994.335
cnt[5]       control_disp|clk     FD1S3DX     Q       cnt[5]     1.108       994.414
cnt[6]       control_disp|clk     FD1S3DX     Q       cnt[6]     1.108       994.414
cnt[7]       control_disp|clk     FD1S3DX     Q       cnt[7]     1.108       994.557
cnt[8]       control_disp|clk     FD1S3DX     Q       cnt[8]     1.108       994.557
cnt[9]       control_disp|clk     FD1S3DX     Q       cnt[9]     1.108       994.699
====================================================================================


Ending Points with Worst Slack
******************************

             Starting                                                   Required            
Instance     Reference            Type        Pin     Net               Time         Slack  
             Clock                                                                          
--------------------------------------------------------------------------------------------
cnt[19]      control_disp|clk     FD1S3DX     D       cnt_3[19]         1000.089     993.986
cnt[17]      control_disp|clk     FD1S3DX     D       cnt_3[17]         1000.089     994.128
cnt[18]      control_disp|clk     FD1S3DX     D       cnt_3[18]         1000.089     994.128
cnt[16]      control_disp|clk     FD1S3DX     D       cnt_3[16]         1000.089     994.271
cnt[20]      control_disp|clk     FD1S3DX     D       un2_cnt_1[20]     999.894      994.408
cnt[14]      control_disp|clk     FD1S3DX     D       cnt_3[14]         1000.089     994.414
cnt[15]      control_disp|clk     FD1S3DX     D       un2_cnt_1[15]     999.894      994.693
cnt[9]       control_disp|clk     FD1S3DX     D       cnt_3[9]          1000.089     994.699
cnt[13]      control_disp|clk     FD1S3DX     D       un2_cnt_1[13]     999.894      994.836
cnt[11]      control_disp|clk     FD1S3DX     D       un2_cnt_1[11]     999.894      994.979
============================================================================================



Worst Path Information
***********************


Path information for path number 1: 
      Requested Period:                      1000.000
    - Setup time:                            -0.089
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         1000.089

    - Propagation time:                      6.103
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     993.986

    Number of logic level(s):                12
    Starting point:                          cnt[0] / Q
    Ending point:                            cnt[19] / D
    The start point is clocked by            control_disp|clk [rising] on pin CK
    The end   point is clocked by            control_disp|clk [rising] on pin CK

Instance / Net                         Pin      Pin               Arrival     No. of    
Name                      Type         Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------
cnt[0]                    FD1S3DX      Q        Out     1.108     1.108       -         
cnt[0]                    Net          -        -       -         -           3         
un2_cnt_1_cry_0_0         CCU2D        A1       In      0.000     1.108       -         
un2_cnt_1_cry_0_0         CCU2D        COUT     Out     1.545     2.652       -         
un2_cnt_1_cry_0           Net          -        -       -         -           1         
un2_cnt_1_cry_1_0         CCU2D        CIN      In      0.000     2.652       -         
un2_cnt_1_cry_1_0         CCU2D        COUT     Out     0.143     2.795       -         
un2_cnt_1_cry_2           Net          -        -       -         -           1         
un2_cnt_1_cry_3_0         CCU2D        CIN      In      0.000     2.795       -         
un2_cnt_1_cry_3_0         CCU2D        COUT     Out     0.143     2.938       -         
un2_cnt_1_cry_4           Net          -        -       -         -           1         
un2_cnt_1_cry_5_0         CCU2D        CIN      In      0.000     2.938       -         
un2_cnt_1_cry_5_0         CCU2D        COUT     Out     0.143     3.081       -         
un2_cnt_1_cry_6           Net          -        -       -         -           1         
un2_cnt_1_cry_7_0         CCU2D        CIN      In      0.000     3.081       -         
un2_cnt_1_cry_7_0         CCU2D        COUT     Out     0.143     3.224       -         
un2_cnt_1_cry_8           Net          -        -       -         -           1         
un2_cnt_1_cry_9_0         CCU2D        CIN      In      0.000     3.224       -         
un2_cnt_1_cry_9_0         CCU2D        COUT     Out     0.143     3.366       -         
un2_cnt_1_cry_10          Net          -        -       -         -           1         
un2_cnt_1_cry_11_0        CCU2D        CIN      In      0.000     3.366       -         
un2_cnt_1_cry_11_0        CCU2D        COUT     Out     0.143     3.509       -         
un2_cnt_1_cry_12          Net          -        -       -         -           1         
un2_cnt_1_cry_13_0        CCU2D        CIN      In      0.000     3.509       -         
un2_cnt_1_cry_13_0        CCU2D        COUT     Out     0.143     3.652       -         
un2_cnt_1_cry_14          Net          -        -       -         -           1         
un2_cnt_1_cry_15_0        CCU2D        CIN      In      0.000     3.652       -         
un2_cnt_1_cry_15_0        CCU2D        COUT     Out     0.143     3.795       -         
un2_cnt_1_cry_16          Net          -        -       -         -           1         
un2_cnt_1_cry_17_0        CCU2D        CIN      In      0.000     3.795       -         
un2_cnt_1_cry_17_0        CCU2D        COUT     Out     0.143     3.938       -         
un2_cnt_1_cry_18          Net          -        -       -         -           1         
un2_cnt_1_cry_19_0        CCU2D        CIN      In      0.000     3.938       -         
un2_cnt_1_cry_19_0        CCU2D        S0       Out     1.549     5.487       -         
un2_cnt_1_cry_19_0_S0     Net          -        -       -         -           1         
cnt_3[19]                 ORCALUT4     B        In      0.000     5.487       -         
cnt_3[19]                 ORCALUT4     Z        Out     0.617     6.103       -         
cnt_3[19]                 Net          -        -       -         -           1         
cnt[19]                   FD1S3DX      D        In      0.000     6.103       -         
========================================================================================



##### END OF TIMING REPORT #####]

Constraints that could not be applied
None

Finished final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 144MB)


Finished timing report (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 144MB)

---------------------------------------
Resource Usage Report
Part: lcmxo2_1200ze-1

Register bits: 21 of 1280 (2%)
PIC Latch:       0
I/O cells:       4


Details:
CCU2D:          11
FD1S3DX:        21
GSR:            1
IB:             2
OB:             2
ORCALUT4:       19
PUR:            1
VHI:            1
VLO:            1
Mapper successful!

At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 31MB peak: 144MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Tue Sep 05 22:00:54 2017

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