Lattice Mapping Report File for Design Module 'esquema_global'



Design Information

Command line:   map -a MachXO2 -p LCMXO2-1200ZE -t TQFP144 -s 1 -oc Commercial
     proyecto_global_proyecto_global.ngd -o
     proyecto_global_proyecto_global_map.ncd -pr
     proyecto_global_proyecto_global.prf -mp proyecto_global_proyecto_global.mrp
     -lpf C:/TFG/exp1_cont/proyecto_global/proyecto_global_proyecto_global_synpl
     ify.lpf -lpf C:/TFG/exp1_cont/proyecto_global.lpf -c 0 -gui -msgset
     C:/TFG/exp1_cont/promote.xml 
Target Vendor:  LATTICE
Target Device:  LCMXO2-1200ZETQFP144
Target Performance:   1
Mapper:  xo2c00,  version:  Diamond Version 3.8.0.115.3
Mapped on:  09/17/17  19:57:50


Design Summary
   Number of registers:     33 out of  1604 (2%)
      PFU registers:           33 out of  1280 (3%)
      PIO registers:            0 out of   324 (0%)
   Number of SLICEs:        53 out of   640 (8%)
      SLICEs as Logic/ROM:     53 out of   640 (8%)
      SLICEs as RAM:            0 out of   480 (0%)
      SLICEs as Carry:         21 out of   640 (3%)
   Number of LUT4s:        105 out of  1280 (8%)
      Number used as logic LUTs:         63
      Number used as distributed RAM:     0
      Number used as ripple logic:       42
      Number used as shift registers:     0
   Number of PIO sites used: 22 + 4(JTAG) out of 108 (24%)
   Number of block RAMs:  0 out of 7 (0%)
   Number of GSRs:  1 out of 1 (100%)
   EFB used :       No
   JTAG used :      No
   Readback used :  No
   Oscillator used :  Yes
   Startup used :   No
   POR :            On
   Bandgap :        On
   Number of Power Controller:  0 out of 1 (0%)
   Number of Dynamic Bank Controller (BCINRD):  0 out of 4 (0%)
   Number of Dynamic Bank Controller (BCLVDSO):  0 out of 1 (0%)
   Number of DCCA:  0 out of 8 (0%)
   Number of DCMA:  0 out of 2 (0%)
   Number of PLLs:  0 out of 1 (0%)
   Number of DQSDLLs:  0 out of 2 (0%)
   Number of CLKDIVC:  0 out of 4 (0%)
   Number of ECLKSYNCA:  0 out of 4 (0%)
   Number of ECLKBRIDGECS:  0 out of 2 (0%)
   Notes:-
      1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
     distributed RAMs) + 2*(Number of ripple logic)
      2. Number of logic LUT4s does not include count of distributed RAM and
     ripple logic.
   Number of clocks:  2
     Net N_25: 11 loads, 11 rising, 0 falling (Driver: I5 )

     Net Q[20]: 6 loads, 6 rising, 0 falling (Driver: I7/FF_0 )
   Number of Clock Enables:  2
     Net N_7: 2 loads, 2 LSLICEs
     Net N_14: 2 loads, 2 LSLICEs
   Number of local set/reset loads for net N_22 merged into GSR:  21
   Number of LSRs:  1
     Net s2: 6 loads, 6 LSLICEs
   Number of nets driven by tri-state buffers:  0
   Top 10 highest fanout non-clock nets:
     Net I7/func_and_inet_4: 21 loads
     Net I7/func_and_inet_6: 21 loads
     Net SL[0]: 10 loads
     Net SL[1]: 10 loads
     Net SL[2]: 10 loads
     Net SL[3]: 10 loads
     Net R[0]: 9 loads
     Net R[1]: 9 loads
     Net R[2]: 9 loads
     Net R[3]: 9 loads




   Number of warnings:  1
   Number of errors:    0
     




Design Errors/Warnings

WARNING - map: Using local reset signal 'N_22' to infer global GSR net.



IO (PIO) Attributes

+---------------------+-----------+-----------+------------+
| IO Name             | Direction | Levelmode | IO         |
|                     |           |  IO_TYPE  | Register   |
+---------------------+-----------+-----------+------------+
| sal1hz              | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| aclr_a1hz           | INPUT     | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| s_led3              | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| s_led2              | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| s_led1              | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| s_led0              | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| seg_g               | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| seg_a               | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| seg_d               | OUTPUT    | LVCMOS33  |            |

+---------------------+-----------+-----------+------------+
| seg_c               | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| seg_b               | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| seg_f               | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| seg_e               | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| dseg_a              | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| dseg_b              | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| dseg_c              | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| dseg_d              | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| dseg_e              | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| dseg_f              | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| dseg_g              | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| in_rest             | INPUT     | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| in_osch             | INPUT     | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+



Removed logic

Block VCC_0 undriven or does not drive anything - clipped.
Block GND_0 undriven or does not drive anything - clipped.
Signal N_8 was merged into signal SL[1]
Signal N_15 was merged into signal ST[1]
Signal N_16 was merged into signal ST[2]
Signal N_9 was merged into signal SL[2]
Signal I7/func_and_inet_5 was merged into signal Q[20]
Signal I7/GND undriven or does not drive anything - clipped.
Signal I7/VCC undriven or does not drive anything - clipped.
Signal I8/VCC undriven or does not drive anything - clipped.
Signal I8/GND undriven or does not drive anything - clipped.
Signal I27/VCC undriven or does not drive anything - clipped.
Signal I27/GND undriven or does not drive anything - clipped.
Signal I43/VCC undriven or does not drive anything - clipped.
Signal I43/GND undriven or does not drive anything - clipped.
Signal VCC undriven or does not drive anything - clipped.
Signal I7/cnt_cia_S1 undriven or does not drive anything - clipped.
Signal I7/cnt_cia_S0 undriven or does not drive anything - clipped.
Signal I7/cnt_10_NC1 undriven or does not drive anything - clipped.
Signal I7/co10 undriven or does not drive anything - clipped.
Signal I8/co1 undriven or does not drive anything - clipped.
Signal I8/cnt_cia_S1_0 undriven or does not drive anything - clipped.
Signal I8/cnt_cia_S0_0 undriven or does not drive anything - clipped.
Signal I27/co1 undriven or does not drive anything - clipped.
Signal I27/cnt_cia_S1_1 undriven or does not drive anything - clipped.

Signal I27/cnt_cia_S0_1 undriven or does not drive anything - clipped.
Signal I43/co1 undriven or does not drive anything - clipped.
Signal I43/cnt_cia_S1_2 undriven or does not drive anything - clipped.
Signal I43/cnt_cia_S0_2 undriven or does not drive anything - clipped.
Signal I5_SEDSTDBY undriven or does not drive anything - clipped.
Block I24 was optimized away.
Block I41 was optimized away.
Block I40 was optimized away.
Block I25 was optimized away.
Block I7/LUT4_2 was optimized away.
Block I7/GND_0 was optimized away.
Block I7/VCC_0 was optimized away.
Block I8/VCC_0 was optimized away.
Block I8/GND_0 was optimized away.
Block I27/VCC_0 was optimized away.
Block I27/GND_0 was optimized away.
Block I43/VCC_0 was optimized away.
Block I43/GND_0 was optimized away.



Memory Usage


     

OSC Summary
-----------

OSC 1:                                     Pin/Node Value
  OSC Instance Name:                                I5
  OSC Type:                                         OSCH
  STDBY Input:                             PIN      N_24
  OSC Output:                              NODE     N_25
  OSC Nominal Frequency (MHz):                      2.08



ASIC Components
---------------

Instance Name: I5
         Type: OSCH



GSR Usage
---------

GSR Component:
   The local reset signal 'N_22' of the design has been inferred as Global Set
        Reset (GSR). The reset signal used for GSR control is 'N_22'.
        

     GSR Property:
   The design components with GSR property set to ENABLED will respond to global
        set reset while the components with GSR property set to DISABLED will
        not.
        





Run Time and Memory Usage
-------------------------

   Total CPU Time: 0 secs  
   Total REAL Time: 0 secs  
   Peak Memory Usage: 34 MB
        






















































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