Lattice Mapping Report File for Design Module 'esquema_con_gpio'



Design Information

Command line:   map -a MachXO2 -p LCMXO2-1200ZE -t TQFP144 -s 1 -oc Commercial
     esquema_con_gpio_esquema_con_gpio.ngd -o
     esquema_con_gpio_esquema_con_gpio_map.ncd -pr
     esquema_con_gpio_esquema_con_gpio.prf -mp
     esquema_con_gpio_esquema_con_gpio.mrp -lpf
     C:/TFG/ex2/esquema_con_gpio/esquema_con_gpio_esquema_con_gpio_synplify.lpf
     -lpf C:/TFG/ex2/esquema_con_gpio.lpf -c 0 -gui -msgset
     C:/TFG/ex2/promote.xml 
Target Vendor:  LATTICE
Target Device:  LCMXO2-1200ZETQFP144
Target Performance:   1
Mapper:  xo2c00,  version:  Diamond Version 3.8.0.115.3
Mapped on:  08/31/17  12:26:34


Design Summary
   Number of registers:    121 out of  1604 (8%)
      PFU registers:          105 out of  1280 (8%)
      PIO registers:           16 out of   324 (5%)
   Number of SLICEs:       202 out of   640 (32%)
      SLICEs as Logic/ROM:    166 out of   640 (26%)
      SLICEs as RAM:           36 out of   480 (8%)
      SLICEs as Carry:         17 out of   640 (3%)
   Number of LUT4s:        402 out of  1280 (31%)
      Number used as logic LUTs:        296
      Number used as distributed RAM:    72
      Number used as ripple logic:       34
      Number used as shift registers:     0
   Number of PIO sites used: 20 + 4(JTAG) out of 108 (22%)
   Number of block RAMs:  6 out of 7 (86%)
   Number of GSRs:  1 out of 1 (100%)
   EFB used :       No
   JTAG used :      No
   Readback used :  No
   Oscillator used :  No
   Startup used :   No
   POR :            On
   Bandgap :        On
   Number of Power Controller:  0 out of 1 (0%)
   Number of Dynamic Bank Controller (BCINRD):  0 out of 4 (0%)
   Number of Dynamic Bank Controller (BCLVDSO):  0 out of 1 (0%)
   Number of DCCA:  0 out of 8 (0%)
   Number of DCMA:  0 out of 2 (0%)
   Number of PLLs:  0 out of 1 (0%)
   Number of DQSDLLs:  0 out of 2 (0%)
   Number of CLKDIVC:  0 out of 4 (0%)
   Number of ECLKSYNCA:  0 out of 4 (0%)
   Number of ECLKBRIDGECS:  0 out of 2 (0%)
   Notes:-
      1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
     distributed RAMs) + 2*(Number of ripple logic)
      2. Number of logic LUT4s does not include count of distributed RAM and
     ripple logic.
   Number of clocks:  2

     Net N_7: 117 loads, 117 rising, 0 falling (Driver: I25/FF_0 )
     Net sal_osc_c: 1 loads, 1 rising, 0 falling (Driver: PIO sal_osc )
   Number of Clock Enables:  11
     Net I1.lm8_inst.gpiosal.genblk3.genblk1.genblk1[0].PIO_DATA19: 8 loads, 0
     LSLICEs
     Net I1.lm8_inst.gpioent.PIO_DATA_RE_EN: 8 loads, 0 LSLICEs
     Net I1/lm8_inst/LM8D_ACK_I: 4 loads, 4 LSLICEs
     Net I1/lm8_inst/LM8/u1_isp8_core/u1_lm8_interrupt/ie_RNO: 1 loads, 1
     LSLICEs
     Net I1/lm8_inst/LM8/u1_isp8_core/u1_lm8_interrupt/im_nxt4: 4 loads, 4
     LSLICEs
     Net I1/lm8_inst/LM8/u1_isp8_core/addr_cyc: 7 loads, 7 LSLICEs
     Net I1/lm8_inst/LM8/data_cyc: 6 loads, 6 LSLICEs
     Net I1/lm8_inst/LM8/u1_isp8_core/u1_lm8_flow_cntl/un8_zero_flag_nxt_i: 1
     loads, 1 LSLICEs
     Net I1/lm8_inst/LM8/u1_isp8_core/u1_lm8_flow_cntl/un8_carry_flag_nxt_i: 1
     loads, 1 LSLICEs
     Net I1/lm8_inst/LM8/prom_enable: 9 loads, 1 LSLICEs
     Net I1/lm8_inst/LM8/u1_isp8_core/page_ptr16: 5 loads, 5 LSLICEs
   Number of local set/reset loads for net I1/lm8_inst/LM8/rst_n merged into
     GSR:  83
   Number of LSRs:  3
     Net I1/lm8_inst/counter[2]: 21 loads, 5 LSLICEs
     Net I1/lm8_inst/LM8/rst_n: 7 loads, 7 LSLICEs
     Net N_1: 2 loads, 2 LSLICEs
   Number of nets driven by tri-state buffers:  0
   Top 10 highest fanout non-clock nets:
     Net I1/lm8_inst/LM8/first_fetch: 59 loads
     Net I1/lm8_inst/LM8/genblk1.u1_isp8_prom/addr10_ff: 36 loads
     Net I1/lm8_inst/LM8/instr[8]: 27 loads
     Net I1/lm8_inst/LM8/instr[9]: 27 loads
     Net I1/lm8_inst/LM8/instr[10]: 26 loads
     Net I1/lm8_inst/LM8/instr[11]: 25 loads
     Net I1/lm8_inst/counter[2]: 24 loads
     Net I1/lm8_inst/LM8/instr[0]: 23 loads
     Net I1/lm8_inst/LM8/u1_isp8_core/u1_lm8_flow_cntl/ret_reg: 22 loads
     Net I1/lm8_inst/LM8/u1_isp8_core/u1_lm8_flow_cntl/rst_exception: 22 loads




   Number of warnings:  7
   Number of errors:    0
     




Design Errors/Warnings

WARNING - map: Using local reset signal 'I1/lm8_inst/LM8/rst_n' to infer global
     GSR net.
WARNING - map: The reset of EBR 'I1/lm8_inst/LM8/genblk1.u1_isp8_prom/pmi_ram_dq
     Enhprom_initsadn18112048p12558403_1_1_0' cannot be controlled. The local
     reset is not connected to any control signal and set to GND. The global
     reset is disabled via GSR property. To control the EBR reset, either
     connect the local reset to a control signal or force the GSR property to be
     enabled.

WARNING - map: The reset of EBR 'I1/lm8_inst/LM8/genblk1.u1_isp8_prom/pmi_ram_dq
     Enhprom_initsadn18112048p12558403_0_0_3' cannot be controlled. The local
     reset is not connected to any control signal and set to GND. The global
     reset is disabled via GSR property. To control the EBR reset, either
     connect the local reset to a control signal or force the GSR property to be
     enabled.
WARNING - map: The reset of EBR 'I1/lm8_inst/LM8/genblk1.u1_isp8_prom/pmi_ram_dq
     Enhprom_initsadn18112048p12558403_0_1_2' cannot be controlled. The local
     reset is not connected to any control signal and set to GND. The global
     reset is disabled via GSR property. To control the EBR reset, either
     connect the local reset to a control signal or force the GSR property to be
     enabled.
WARNING - map: The reset of EBR 'I1/lm8_inst/LM8/genblk1.u1_isp8_prom/pmi_ram_dq
     Enhprom_initsadn18112048p12558403_1_0_1' cannot be controlled. The local
     reset is not connected to any control signal and set to GND. The global
     reset is disabled via GSR property. To control the EBR reset, either
     connect the local reset to a control signal or force the GSR property to be
     enabled.
WARNING - map: The reset of EBR 'I1/lm8_inst/LM8/genblk3.u1_scratchpad/pmi_ram_d
     qEnhscratchpad_initsadn8112048p12b46f23_0_1_0' cannot be controlled. The
     local reset is not connected to any control signal and set to GND. The
     global reset is disabled via GSR property. To control the EBR reset, either
     connect the local reset to a control signal or force the GSR property to be
     enabled.
WARNING - map: The reset of EBR 'I1/lm8_inst/LM8/genblk3.u1_scratchpad/pmi_ram_d
     qEnhscratchpad_initsadn8112048p12b46f23_0_0_1' cannot be controlled. The
     local reset is not connected to any control signal and set to GND. The
     global reset is disabled via GSR property. To control the EBR reset, either
     connect the local reset to a control signal or force the GSR property to be
     enabled.



IO (PIO) Attributes

+---------------------+-----------+-----------+------------+
| IO Name             | Direction | Levelmode | IO         |
|                     |           |  IO_TYPE  | Register   |
+---------------------+-----------+-----------+------------+
| s7                  | OUTPUT    | LVCMOS33  | OUT        |
+---------------------+-----------+-----------+------------+
| e7                  | INPUT     | LVCMOS33  | IN         |
+---------------------+-----------+-----------+------------+
| sal_osc             | INPUT     | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| enc_osc             | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| ps                  | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| s0                  | OUTPUT    | LVCMOS33  | OUT        |
+---------------------+-----------+-----------+------------+
| s1                  | OUTPUT    | LVCMOS33  | OUT        |
+---------------------+-----------+-----------+------------+
| s2                  | OUTPUT    | LVCMOS33  | OUT        |
+---------------------+-----------+-----------+------------+
| s3                  | OUTPUT    | LVCMOS33  | OUT        |
+---------------------+-----------+-----------+------------+

| s4                  | OUTPUT    | LVCMOS33  | OUT        |
+---------------------+-----------+-----------+------------+
| s5                  | OUTPUT    | LVCMOS33  | OUT        |
+---------------------+-----------+-----------+------------+
| s6                  | OUTPUT    | LVCMOS33  | OUT        |
+---------------------+-----------+-----------+------------+
| pe                  | INPUT     | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| e3                  | INPUT     | LVCMOS33  | IN         |
+---------------------+-----------+-----------+------------+
| e2                  | INPUT     | LVCMOS33  | IN         |
+---------------------+-----------+-----------+------------+
| e1                  | INPUT     | LVCMOS33  | IN         |
+---------------------+-----------+-----------+------------+
| e0                  | INPUT     | LVCMOS33  | IN         |
+---------------------+-----------+-----------+------------+
| e4                  | INPUT     | LVCMOS33  | IN         |
+---------------------+-----------+-----------+------------+
| e5                  | INPUT     | LVCMOS33  | IN         |
+---------------------+-----------+-----------+------------+
| e6                  | INPUT     | LVCMOS33  | IN         |
+---------------------+-----------+-----------+------------+



Removed logic

Block GND undriven or does not drive anything - clipped.
Block I1/lm8_inst/GND undriven or does not drive anything - clipped.
Block I1/lm8_inst/VCC undriven or does not drive anything - clipped.
Block I1/lm8_inst/arbiter/VCC undriven or does not drive anything - clipped.
Block I1/lm8_inst/LM8/u1_isp8_core/GND undriven or does not drive anything -
     clipped.
Block I1/lm8_inst/LM8/u1_isp8_core/u1_lm8_idec/GND undriven or does not drive
     anything - clipped.
Block I1/lm8_inst/LM8/u1_isp8_core/u1_lm8_alu/GND undriven or does not drive
     anything - clipped.
Block I1/lm8_inst/LM8/u1_isp8_core/u1_lm8_alu/u1_addsub8/scuba_vhi_inst undriven
     or does not drive anything - clipped.
Block I1/lm8_inst/LM8/u1_isp8_core/u1_lm8_alu/u1_addsub8/addsubd undriven or
     does not drive anything - clipped.
Block I1/lm8_inst/LM8/u1_isp8_core/u1_lm8_flow_cntl/genblk3.u1_lm8_stkmem/mem_0_
     0/RAM1 undriven or does not drive anything - clipped.
Block I1/lm8_inst/LM8/u1_isp8_core/u1_lm8_cntl_u1/GND undriven or does not drive
     anything - clipped.
Block I1/lm8_inst/LM8/u1_isp8_core/u1_lm8_cntl_u1/VCC undriven or does not drive
     anything - clipped.
Block I1/lm8_inst/LM8/u1_isp8_core/u1_lm8_interrupt/VCC undriven or does not
     drive anything - clipped.
Block I1/lm8_inst/gpioent/GND undriven or does not drive anything - clipped.
Block I1/lm8_inst/gpioent/VCC undriven or does not drive anything - clipped.
Block I1/lm8_inst/gpiosal/GND undriven or does not drive anything - clipped.
Block I1/lm8_inst/gpiosal/VCC undriven or does not drive anything - clipped.
Signal N_1_i was merged into signal N_1
Signal I1.lm8_inst.counter_i[2] was merged into signal I1/lm8_inst/counter[2]
Signal I1/lm8_inst/LM8/rst_n_i was merged into signal I1/lm8_inst/LM8/rst_n
Signal I1/lm8_inst/LM8/genblk1.u1_isp8_prom/wren_inv_g was merged into signal

     I1/lm8_inst/LM8/prom_enable
Signal I1/lm8_inst/LM8/u1_isp8_core/u1_lm8_alu/u1_addsub8/add_sub_inv was merged
     into signal I1/lm8_inst/LM8/u1_isp8_core/u1_lm8_alu/add_sel_i
Signal I1/lm8_inst/LM8/u1_isp8_core/u1_lm8_flow_cntl/genblk3.u1_lm8_stkmem/dec0_
     wre3 was merged into signal
     I1/lm8_inst/LM8/u1_isp8_core/u1_lm8_flow_cntl/stack_ptr_nxt9
Signal I1/lm8_inst/LM8/VCC undriven or does not drive anything - clipped.
Signal I1/lm8_inst/LM8/GND undriven or does not drive anything - clipped.
Signal I1/lm8_inst/LM8/genblk1.u1_isp8_prom/wren_inv undriven or does not drive
     anything - clipped.
Signal I1/lm8_inst/LM8/genblk3.u1_scratchpad/scuba_vlo undriven or does not
     drive anything - clipped.
Signal I1/lm8_inst/LM8/genblk3.u1_scratchpad/scuba_vhi undriven or does not
     drive anything - clipped.
Signal I1/lm8_inst/LM8/genblk1.u1_isp8_prom/scuba_vlo undriven or does not drive
     anything - clipped.
Signal I1/lm8_inst/LM8/genblk1.u1_isp8_prom/scuba_vhi undriven or does not drive
     anything - clipped.
Signal I1/lm8_inst/LM8/u1_isp8_core/VCC undriven or does not drive anything -
     clipped.
Signal I1/lm8_inst/LM8/u1_isp8_core/genblk6.genblk1.u2_lm8_rfmem/scuba_vhi
     undriven or does not drive anything - clipped.
Signal I1/lm8_inst/LM8/u1_isp8_core/genblk6.genblk1.u1_lm8_rfmem/scuba_vhi
     undriven or does not drive anything - clipped.
Signal I1/lm8_inst/LM8/u1_isp8_core/u1_lm8_alu/u1_addsub8/scuba_vlo undriven or
     does not drive anything - clipped.
Signal I1/lm8_inst/LM8/u1_isp8_core/u1_lm8_flow_cntl/GND undriven or does not
     drive anything - clipped.
Signal I1/lm8_inst/LM8/u1_isp8_core/u1_lm8_flow_cntl/VCC undriven or does not
     drive anything - clipped.
Signal I1/lm8_inst/LM8/u1_isp8_core/u1_lm8_flow_cntl/genblk3.u1_lm8_stkmem/scuba
     _vhi undriven or does not drive anything - clipped.
Signal I25/GND undriven or does not drive anything - clipped.
Signal I25/VCC undriven or does not drive anything - clipped.
Signal I1/lm8_inst/LM8/u1_isp8_core/GND undriven or does not drive anything -
     clipped.
Signal I1/lm8_inst/LM8/u1_isp8_core/u1_lm8_alu/u1_addsub8/scuba_vhi undriven or
     does not drive anything - clipped.
Signal I1/lm8_inst/LM8/u1_isp8_core/u1_lm8_alu/u1_addsub8/addsub_0/S0 undriven
     or does not drive anything - clipped.
Signal I1/lm8_inst/LM8/u1_isp8_core/u1_lm8_alu/u1_addsub8/precin_inst30/S1
     undriven or does not drive anything - clipped.
Signal I1/lm8_inst/LM8/u1_isp8_core/u1_lm8_alu/u1_addsub8/precin_inst30/S0
     undriven or does not drive anything - clipped.
Signal I1/lm8_inst/LM8/u1_isp8_core/u1_lm8_alu/u1_addsub8/addsubd/S1 undriven or
     does not drive anything - clipped.
Signal I1/lm8_inst/LM8/u1_isp8_core/u1_lm8_alu/u1_addsub8/co4d undriven or does
     not drive anything - clipped.
Signal I1/lm8_inst/LM8/u1_isp8_core/u1_lm8_alu/u1_addsub8/addsubd/COUT undriven
     or does not drive anything - clipped.
Signal I1/lm8_inst/LM8/u1_isp8_core/u1_lm8_alu/u1_addsub8/co4 undriven or does
     not drive anything - clipped.
Signal I1/lm8_inst/LM8/u1_isp8_core/u1_lm8_flow_cntl/un1_stack_ptr_s_3_0_S1
     undriven or does not drive anything - clipped.
Signal I1/lm8_inst/LM8/u1_isp8_core/u1_lm8_flow_cntl/un1_stack_ptr_s_3_0_COUT
     undriven or does not drive anything - clipped.

Signal
     I1/lm8_inst/LM8/u1_isp8_core/u1_lm8_flow_cntl/potential_address_cry_0_0_S1
     undriven or does not drive anything - clipped.
Signal
     I1/lm8_inst/LM8/u1_isp8_core/u1_lm8_flow_cntl/potential_address_cry_0_0_S0
     undriven or does not drive anything - clipped.
Signal I1/lm8_inst/LM8/u1_isp8_core/u1_lm8_flow_cntl/N_3 undriven or does not
     drive anything - clipped.
Signal I1/lm8_inst/LM8/u1_isp8_core/u1_lm8_flow_cntl/potential_address_cry_9_0_C
     OUT undriven or does not drive anything - clipped.
Signal I1/lm8_inst/LM8/u1_isp8_core/u1_lm8_flow_cntl/genblk3.u1_lm8_stkmem/mem_0
     _0/DO2 undriven or does not drive anything - clipped.
Signal I1/lm8_inst/LM8/u1_isp8_core/u1_lm8_flow_cntl/genblk3.u1_lm8_stkmem/mem_0
     _0/DO3 undriven or does not drive anything - clipped.
Signal I1/lm8_inst/LM8/u1_isp8_core/u1_lm8_flow_cntl/genblk3.u1_lm8_stkmem/mem_0
     _0/DO1 undriven or does not drive anything - clipped.
Signal I1/lm8_inst/LM8/u1_isp8_core/u1_lm8_flow_cntl/un1_stack_ptr_cry_0_0_S1
     undriven or does not drive anything - clipped.
Signal I1/lm8_inst/LM8/u1_isp8_core/u1_lm8_flow_cntl/un1_stack_ptr_cry_0_0_S0
     undriven or does not drive anything - clipped.
Signal I1/lm8_inst/LM8/u1_isp8_core/u1_lm8_flow_cntl/N_2 undriven or does not
     drive anything - clipped.
Signal I25/cnt_cia_S1 undriven or does not drive anything - clipped.
Signal I25/cnt_cia_S0 undriven or does not drive anything - clipped.
Signal I25/cnt_0_NC1 undriven or does not drive anything - clipped.
Signal I25/co0 undriven or does not drive anything - clipped.
Block I22_RNID9F2 was optimized away.
Block I1/lm8_inst/counter_RNIEGJ[2] was optimized away.
Block I1/lm8_inst/LM8/rst_n_RNI9FK2 was optimized away.
Block I1/lm8_inst/LM8/genblk1.u1_isp8_prom/AND2_t0 was optimized away.
Block I1/lm8_inst/LM8/u1_isp8_core/u1_lm8_alu/u1_addsub8/INV_0 was optimized
     away.
Block I1/lm8_inst/LM8/u1_isp8_core/u1_lm8_flow_cntl/genblk3.u1_lm8_stkmem/LUT4_0
     was optimized away.
Block I1/lm8_inst/LM8/VCC was optimized away.
Block I1/lm8_inst/LM8/GND was optimized away.
Block I1/lm8_inst/LM8/genblk1.u1_isp8_prom/INV_0 was optimized away.
Block I1/lm8_inst/LM8/genblk3.u1_scratchpad/scuba_vlo_inst was optimized away.
Block I1/lm8_inst/LM8/genblk3.u1_scratchpad/scuba_vhi_inst was optimized away.
Block I1/lm8_inst/LM8/genblk1.u1_isp8_prom/scuba_vlo_inst was optimized away.
Block I1/lm8_inst/LM8/genblk1.u1_isp8_prom/scuba_vhi_inst was optimized away.
Block I1/lm8_inst/LM8/u1_isp8_core/VCC was optimized away.
Block I1/lm8_inst/LM8/u1_isp8_core/genblk6.genblk1.u2_lm8_rfmem/scuba_vhi_inst
     was optimized away.
Block I1/lm8_inst/LM8/u1_isp8_core/genblk6.genblk1.u1_lm8_rfmem/scuba_vhi_inst
     was optimized away.
Block I1/lm8_inst/LM8/u1_isp8_core/u1_lm8_alu/u1_addsub8/scuba_vlo_inst was
     optimized away.
Block I1/lm8_inst/LM8/u1_isp8_core/u1_lm8_flow_cntl/GND was optimized away.
Block I1/lm8_inst/LM8/u1_isp8_core/u1_lm8_flow_cntl/VCC was optimized away.
Block I1/lm8_inst/LM8/u1_isp8_core/u1_lm8_flow_cntl/genblk3.u1_lm8_stkmem/scuba_
     vhi_inst was optimized away.
Block I25/GND was optimized away.
Block I25/VCC was optimized away.





Memory Usage

/I1/lm8_inst/LM8/genblk1.u1_isp8_prom:
    EBRs: 4
    RAM SLICEs: 0
    Logic SLICEs: 4
    PFU Registers: 0
    -Contains EBR pmi_ram_dqEnhprom_initsadn18112048p12558403_1_1_0:  TYPE=
         DP8KC,  Width_A= 9,  Depth_A= 1024,  REGMODE_A= NOREG,  REGMODE_B=
         NOREG,  RESETMODE= ASYNC,  ASYNC_RESET_RELEASE= SYNC,  WRITEMODE_A=
         NORMAL,  WRITEMODE_B= NORMAL,  GSR= DISABLED,  MEM_INIT_FILE=
         prom_init.mem,  MEM_LPC_FILE=
         pmi_ram_dqEnhprom_initsadn18112048p12558403__PMIS__2048__18__18H
    -Contains EBR pmi_ram_dqEnhprom_initsadn18112048p12558403_0_0_3:  TYPE=
         DP8KC,  Width_A= 9,  Depth_A= 1024,  REGMODE_A= NOREG,  REGMODE_B=
         NOREG,  RESETMODE= ASYNC,  ASYNC_RESET_RELEASE= SYNC,  WRITEMODE_A=
         NORMAL,  WRITEMODE_B= NORMAL,  GSR= DISABLED,  MEM_INIT_FILE=
         prom_init.mem,  MEM_LPC_FILE=
         pmi_ram_dqEnhprom_initsadn18112048p12558403__PMIS__2048__18__18H
    -Contains EBR pmi_ram_dqEnhprom_initsadn18112048p12558403_0_1_2:  TYPE=
         DP8KC,  Width_A= 9,  Depth_A= 1024,  REGMODE_A= NOREG,  REGMODE_B=
         NOREG,  RESETMODE= ASYNC,  ASYNC_RESET_RELEASE= SYNC,  WRITEMODE_A=
         NORMAL,  WRITEMODE_B= NORMAL,  GSR= DISABLED,  MEM_INIT_FILE=
         prom_init.mem,  MEM_LPC_FILE=
         pmi_ram_dqEnhprom_initsadn18112048p12558403__PMIS__2048__18__18H
    -Contains EBR pmi_ram_dqEnhprom_initsadn18112048p12558403_1_0_1:  TYPE=
         DP8KC,  Width_A= 9,  Depth_A= 1024,  REGMODE_A= NOREG,  REGMODE_B=
         NOREG,  RESETMODE= ASYNC,  ASYNC_RESET_RELEASE= SYNC,  WRITEMODE_A=
         NORMAL,  WRITEMODE_B= NORMAL,  GSR= DISABLED,  MEM_INIT_FILE=
         prom_init.mem,  MEM_LPC_FILE=
         pmi_ram_dqEnhprom_initsadn18112048p12558403__PMIS__2048__18__18H
/I1/lm8_inst/LM8/genblk3.u1_scratchpad:
    EBRs: 2
    RAM SLICEs: 0
    Logic SLICEs: 0
    PFU Registers: 0
    -Contains EBR pmi_ram_dqEnhscratchpad_initsadn8112048p12b46f23_0_1_0:  TYPE=
         DP8KC,  Width_A= 4,  Depth_A= 2048,  REGMODE_A= NOREG,  REGMODE_B=
         NOREG,  RESETMODE= ASYNC,  ASYNC_RESET_RELEASE= SYNC,  WRITEMODE_A=
         NORMAL,  WRITEMODE_B= NORMAL,  GSR= DISABLED,  MEM_INIT_FILE=
         scratchpad_init.mem,  MEM_LPC_FILE=
         pmi_ram_dqEnhscratchpad_initsadn8112048p12b46f23__PMIS__2048__8__8H
    -Contains EBR pmi_ram_dqEnhscratchpad_initsadn8112048p12b46f23_0_0_1:  TYPE=
         DP8KC,  Width_A= 4,  Depth_A= 2048,  REGMODE_A= NOREG,  REGMODE_B=
         NOREG,  RESETMODE= ASYNC,  ASYNC_RESET_RELEASE= SYNC,  WRITEMODE_A=
         NORMAL,  WRITEMODE_B= NORMAL,  GSR= DISABLED,  MEM_INIT_FILE=
         scratchpad_init.mem,  MEM_LPC_FILE=
         pmi_ram_dqEnhscratchpad_initsadn8112048p12b46f23__PMIS__2048__8__8H
/I1/lm8_inst/LM8/u1_isp8_core/genblk6.genblk1.u1_lm8_rfmem:
    EBRs: 0
    RAM SLICEs: 12
    Logic SLICEs: 0
    PFU Registers: 0
/I1/lm8_inst/LM8/u1_isp8_core/genblk6.genblk1.u2_lm8_rfmem:
    EBRs: 0
    RAM SLICEs: 12
    Logic SLICEs: 0

    PFU Registers: 0
/I1/lm8_inst/LM8/u1_isp8_core/u1_lm8_flow_cntl/genblk3.u1_lm8_stkmem:
    EBRs: 0
    RAM SLICEs: 11
    Logic SLICEs: 0
    PFU Registers: 0
/I1/lm8_inst/LM8/u1_isp8_core/u1_lm8_flow_cntl/genblk3.u1_lm8_stkmem/mem_0_0/RAM
     W:
    EBRs: 0
    RAM SLICEs: 1
    Logic SLICEs: 0
    PFU Registers: 0

     



ASIC Components
---------------

Instance Name: I1/lm8_inst/LM8/genblk1.u1_isp8_prom/pmi_ram_dqEnhprom_initsadn18
     112048p12558403_1_1_0
         Type: DP8KC
Instance Name: I1/lm8_inst/LM8/genblk1.u1_isp8_prom/pmi_ram_dqEnhprom_initsadn18
     112048p12558403_0_0_3
         Type: DP8KC
Instance Name: I1/lm8_inst/LM8/genblk1.u1_isp8_prom/pmi_ram_dqEnhprom_initsadn18
     112048p12558403_0_1_2
         Type: DP8KC
Instance Name: I1/lm8_inst/LM8/genblk1.u1_isp8_prom/pmi_ram_dqEnhprom_initsadn18
     112048p12558403_1_0_1
         Type: DP8KC
Instance Name: I1/lm8_inst/LM8/genblk3.u1_scratchpad/pmi_ram_dqEnhscratchpad_ini
     tsadn8112048p12b46f23_0_1_0
         Type: DP8KC
Instance Name: I1/lm8_inst/LM8/genblk3.u1_scratchpad/pmi_ram_dqEnhscratchpad_ini
     tsadn8112048p12b46f23_0_0_1
         Type: DP8KC



GSR Usage
---------

GSR Component:
   The local reset signal 'I1/lm8_inst/LM8/rst_n' of the design has been
        inferred as Global Set Reset (GSR). The reset signal used for GSR
        control is 'I1/lm8_inst/LM8/rst_n'.
        

     GSR Property:
   The design components with GSR property set to ENABLED will respond to global
        set reset while the components with GSR property set to DISABLED will
        not.
        

     Components on inferred reset domain with GSR Property disabled
--------------------------------------------------------------

     These components have the GSR property set to DISABLED and are on the

     inferred reset domain. The components will respond to the reset signal
     'I1/lm8_inst/LM8/rst_n' via the local reset on the component and not the
     GSR component.

     Type and number of components of the type: 
   Register = 12 

     Type and instance name of component: 
   Register : I1/lm8_inst/LM8/u1_isp8_core/u1_lm8_flow_cntl/rst_n_reg
   Register : I1/lm8_inst/LM8/ext_wb_state
   Register : I1/lm8_inst/LM8/save_data[7]
   Register : I1/lm8_inst/LM8/u1_isp8_core/u1_lm8_flow_cntl/rst_exception
   Register : I1/lm8_inst/LM8/save_data[0]
   Register : I1/lm8_inst/LM8/save_data[1]
   Register : I1/lm8_inst/LM8/save_data[2]
   Register : I1/lm8_inst/LM8/save_data[3]
   Register : I1/lm8_inst/LM8/save_data[4]
   Register : I1/lm8_inst/LM8/save_data[5]
   Register : I1/lm8_inst/LM8/save_data[6]
   Register : I1/lm8_inst/LM8/genblk2.D_ACK_I_d



Run Time and Memory Usage
-------------------------

   Total CPU Time: 0 secs  
   Total REAL Time: 0 secs  
   Peak Memory Usage: 36 MB
        































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