Project Settings |
---|
Project Name | proj_1 | Implementation Name | control_disp |
Top Module | work.control_disp | Pipelining | 1 |
Retiming | 0 | Resource Sharing | 1 |
Fanout Guide | 1000 | Disable I/O Insertion | 0 |
Disable Sequential Optimizations | 0 | Clock Conversion | 1 |
Run Status |
Job Name |
Status |
|
|
|
CPU Time |
Real Time |
Memory |
Date/Time |
(compiler) | Complete |
6 |
1 |
0 |
- |
0m:01s |
- |
05/09/2017 22:00:51 |
(premap) | Complete |
2 |
1 |
0 |
0m:00s |
0m:00s |
141MB |
05/09/2017 22:00:53 |
(fpga_mapper) | Complete |
9 |
1 |
0 |
0m:01s |
0m:01s |
144MB |
05/09/2017 22:00:54 |
Multi-srs Generator |
Complete | | | | | | | 05/09/2017 22:00:52 |
Area Summary |
|
Register bits | 21 |
I/O cells | 4 |
Block RAMs
(v_ram) | 0 |
DSPs
(dsp_used) | 0 |
ORCA LUTs
(total_luts) | 19 |
| |
Timing Summary |
|
Clock Name | Req Freq | Est Freq | Slack |
control_disp|clk | 1.0 MHz | 166.3 MHz | 993.986 |
Optimizations Summary |
Combined Clock Conversion | 1 / 0 |
| |
|