Project Settings
Project Name proj_1 Implementation Name proyecto_global
Top Module esquema_global Pipelining 1
Retiming 0 Resource Sharing 1
Fanout Guide 1000 Disable I/O Insertion 0
Disable Sequential Optimizations 0 Clock Conversion 1

Run Status
Job Name Status CPU Time Real Time Memory Date/Time
(compiler)Complete 22 76 0 - 0m:02s - 17/09/2017
19:57:43
(premap)Complete 2 1 0 0m:00s 0m:00s 141MB 17/09/2017
19:57:45
(fpga_mapper)Complete 14 6 0 0m:01s 0m:01s 144MB 17/09/2017
19:57:47
Multi-srs Generator Complete17/09/2017
19:57:44

Area Summary
Register bits 33 I/O cells 22
Block RAMs (v_ram) 0 DSPs (dsp_used) 0
ORCA LUTs (total_luts) 14

Timing Summary
Clock NameReq FreqEst FreqSlack
divfrec1|tdataout20_derived_clock2.1 MHz334.2 MHz477.777
esquema_global|N_25_inferred_clock2.1 MHz201.0 MHz475.795
System1.0 MHz1.9 MHz480.298

Optimizations Summary
Combined Clock Conversion 1 / 1