Project Settings
Project Name proj_1 Implementation Name DEC_DISP
Top Module DEC_DISP Pipelining 1
Retiming 0 Resource Sharing 1
Fanout Guide 1000 Disable I/O Insertion 0
Disable Sequential Optimizations 0 Clock Conversion 1

Run Status
Job Name Status CPU Time Real Time Memory Date/Time
(compiler)Complete 6 0 0 - 0m:01s - 30/08/2017
0:39:57
(premap)Complete 2 0 0 0m:00s 0m:01s 140MB 30/08/2017
0:40:00
(fpga_mapper)Complete 10 2 0 0m:01s 0m:01s 144MB 30/08/2017
0:40:02
Multi-srs Generator Complete30/08/2017
0:39:58

Area Summary
Register bits 0 I/O cells 12
Block RAMs (v_ram) 0 DSPs (dsp_used) 0
ORCA LUTs (total_luts) 7

Optimizations Summary
Combined Clock Conversion 0 / 0