PAR: Place And Route Diamond Version 3.8.0.115.3. Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2016 Lattice Semiconductor Corporation, All rights reserved. Wed Sep 06 01:13:47 2017 C:/lscc/diamond/3.8/ispfpga\bin\nt\par -f esquema_con_gpio_esquema_con_gpio.p2t esquema_con_gpio_esquema_con_gpio_map.ncd esquema_con_gpio_esquema_con_gpio.dir esquema_con_gpio_esquema_con_gpio.prf -gui -msgset C:/TFG/ex2/promote.xml Preference file: esquema_con_gpio_esquema_con_gpio.prf. Cost Table Summary Level/ Number Worst Timing Worst Timing Run NCD Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status ---------- -------- ----- ------ ----------- ----------- ---- ------ 5_1 * 0 - - - - 05 Complete * : Design saved. Total (real) run time for 1-seed: 5 secs par done! Lattice Place and Route Report for Design "esquema_con_gpio_esquema_con_gpio_map.ncd" Wed Sep 06 01:13:47 2017 Best Par Run PAR: Place And Route Diamond Version 3.8.0.115.3. Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset C:/TFG/ex2/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF esquema_con_gpio_esquema_con_gpio_map.ncd esquema_con_gpio_esquema_con_gpio.dir/5_1.ncd esquema_con_gpio_esquema_con_gpio.prf Preference file: esquema_con_gpio_esquema_con_gpio.prf. Placement level-cost: 5-1. Routing Iterations: 6 Loading design for application par from file esquema_con_gpio_esquema_con_gpio_map.ncd. Design name: esquema_con_gpio NCD version: 3.3 Vendor: LATTICE Device: LCMXO2-1200ZE Package: TQFP144 Performance: 1 Loading device for application par from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.8/ispfpga. Package Status: Final Version 1.42. Performance Hardware Data Status: Final Version 34.4. License checked out. Ignore Preference Error(s): True Device utilization summary: PIO (prelim) 20+4(JTAG)/108 22% used 20+4(JTAG)/108 22% bonded IOLOGIC 16/108 14% used SLICE 202/640 31% used GSR 1/1 100% used EBR 6/7 85% used INFO: Design contains EBR with ASYNC Reset Mode that has a limitation: The use of the EBR block asynchronous reset requires that certain timing be met between the clock and the reset within the memory block. See the device specific data sheet for additional details. INFO: Design contains pre-loadable EBR during configuration that has a requirement: Since the GSR is disabled for the EBR, make sure write enable and chip enable are inactive during wake-up, so that the pre-loaded initialization values will not be corrupted during wake-up state. Number of Signals: 629 Number of Connections: 1983 Pin Constraint Summary: 20 out of 20 pins locked (100% locked). The following 1 signal is selected to use the primary clock routing resources: N_7 (driver: I25/SLICE_0, clk load #: 117) The following 1 signal is selected to use the secondary clock routing resources: I1/lm8_inst/counter[2] (driver: I1/lm8_inst/SLICE_109, clk load #: 0, sr load #: 21, ce load #: 0) Signal I1/lm8_inst/LM8/rst_n is selected as Global Set/Reset. Starting Placer Phase 0. ......... Finished Placer Phase 0. REAL time: 0 secs Starting Placer Phase 1. .................... Placer score = 104383. Finished Placer Phase 1. REAL time: 3 secs Starting Placer Phase 2. . Placer score = 102491 Finished Placer Phase 2. REAL time: 4 secs Clock Report Global Clock Resources: CLK_PIN : 0 out of 8 (0%) PLL : 0 out of 1 (0%) DCM : 0 out of 2 (0%) DCC : 0 out of 8 (0%) Quadrants All (TL, TR, BL, BR) - Global Clocks: PRIMARY "N_7" from Q0 on comp "I25/SLICE_0" on site "R2C13B", clk load = 117 SECONDARY "I1/lm8_inst/counter[2]" from Q0 on comp "I1/lm8_inst/SLICE_109" on site "R7C12D", clk load = 0, ce load = 0, sr load = 21 PRIMARY : 1 out of 8 (12%) SECONDARY: 1 out of 8 (12%) Edge Clocks: No edge clock selected. I/O Usage Summary (final): 20 + 4(JTAG) out of 108 (22.2%) PIO sites used. 20 + 4(JTAG) out of 108 (22.2%) bonded PIO sites used. Number of PIO comps: 20; differential: 0. Number of Vref pins used: 0. I/O Bank Usage Summary: +----------+----------------+------------+-----------+ | I/O Bank | Usage | Bank Vccio | Bank Vref | +----------+----------------+------------+-----------+ | 0 | 0 / 28 ( 0%) | - | - | | 1 | 17 / 26 ( 65%) | 3.3V | - | | 2 | 0 / 28 ( 0%) | - | - | | 3 | 3 / 26 ( 11%) | 3.3V | - | +----------+----------------+------------+-----------+ Total placer CPU time: 3 secs Dumping design to file esquema_con_gpio_esquema_con_gpio.dir/5_1.ncd. ----------------------------------------------------------------- INFO - par: ASE feature is off due to non timing-driven settings. ----------------------------------------------------------------- 0 connections routed; 1983 unrouted. Starting router resource preassignment WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew. Signal=sal_osc_c loads=1 clock_loads=1 Completed router resource preassignment. Real time: 4 secs Start NBR router at 01:13:51 09/06/17 ***************************************************************** Info: NBR allows conflicts(one node used by more than one signal) in the earlier iterations. In each iteration, it tries to solve the conflicts while keeping the critical connections routed as short as possible. The routing process is said to be completed when no conflicts exist and all connections are routed. Note: NBR uses a different method to calculate timing slacks. The worst slack and total negative slack may not be the same as that in TRCE report. You should always run TRCE to verify your design. ***************************************************************** Start NBR special constraint process at 01:13:51 09/06/17 Start NBR section for initial routing at 01:13:51 09/06/17 Level 4, iteration 1 17(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; real time: 5 secs Info: Initial congestion level at 75% usage is 0 Info: Initial congestion area at 75% usage is 0 (0.00%) Start NBR section for normal routing at 01:13:52 09/06/17 Level 4, iteration 1 4(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; real time: 5 secs Level 4, iteration 2 3(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; real time: 5 secs Level 4, iteration 3 0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; real time: 5 secs Start NBR section for re-routing at 01:13:52 09/06/17 Level 4, iteration 1 0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; real time: 5 secs Start NBR section for post-routing at 01:13:52 09/06/17 End NBR router with 0 unrouted connection NBR Summary ----------- Number of unrouted connections : 0 (0.00%) Number of connections with timing violations : 0 (0.00%) Estimated worst slack<setup> : <n/a> Timing score<setup> : 0 ----------- Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored. WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew. Signal=sal_osc_c loads=1 clock_loads=1 Total CPU time 5 secs Total REAL time: 5 secs Completely routed. End of route. 1983 routed (100.00%); 0 unrouted. Hold time timing score: 0, hold timing errors: 0 Timing score: 0 Dumping design to file esquema_con_gpio_esquema_con_gpio.dir/5_1.ncd. All signals are completely routed. PAR_SUMMARY::Run status = completed PAR_SUMMARY::Number of unrouted conns = 0 PAR_SUMMARY::Worst slack<setup/<ns>> = <n/a> PAR_SUMMARY::Timing score<setup/<ns>> = <n/a> PAR_SUMMARY::Worst slack<hold /<ns>> = <n/a> PAR_SUMMARY::Timing score<hold /<ns>> = <n/a> PAR_SUMMARY::Number of errors = 0 Total CPU time to completion: 5 secs Total REAL time to completion: 6 secs par done! Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2016 Lattice Semiconductor Corporation, All rights reserved.