Project Settings |
---|
Project Name | proj_1 | Implementation Name | proyecto_global |
Top Module | esquema_global | Pipelining | 1 |
Retiming | 0 | Resource Sharing | 1 |
Fanout Guide | 1000 | Disable I/O Insertion | 0 |
Disable Sequential Optimizations | 0 | Clock Conversion | 1 |
Run Status |
Job Name |
Status |
|
|
|
CPU Time |
Real Time |
Memory |
Date/Time |
(compiler) | Complete |
29 |
98 |
0 |
- |
0m:01s |
- |
21/09/2017 5:01:54 |
(premap) | Complete |
2 |
4 |
0 |
0m:00s |
0m:00s |
141MB |
21/09/2017 5:01:56 |
(fpga_mapper) | Complete |
13 |
11 |
0 |
0m:01s |
0m:01s |
145MB |
21/09/2017 5:01:59 |
Multi-srs Generator |
Complete | | | | 0m:01s | | | 21/09/2017 5:01:56 |
Area Summary |
|
Register bits | 60 |
I/O cells | 25 |
Block RAMs
(v_ram) | 0 |
DSPs
(dsp_used) | 0 |
ORCA LUTs
(total_luts) | 36 |
| |
Timing Summary |
|
Clock Name | Req Freq | Est Freq | Slack |
esquema_global|N_25_inferred_clock | 2.1 MHz | 201.0 MHz | 475.795 |
esquema_global|N_28_inferred_clock | 1.0 MHz | 165.2 MHz | 993.946 |
esquema_global|clk_ext_sal | 1.0 MHz | 254.8 MHz | 996.075 |
pll1|CLKOS3_inferred_clock | 1.0 MHz | 334.2 MHz | 997.007 |
System | 1.0 MHz | 1.9 MHz | 480.664 |
Optimizations Summary |
Combined Clock Conversion | 1 / 3 |
| |
|