Setting log file to 'C:/TFG/exp6/esquema_con_gpio/hdla_gen_hierarchy.html'. Starting: parse design source files (VHDL-1481) Analyzing VHDL file C:/lscc/diamond/3.8/ispfpga/vhdl_packages/standard.vhd INFO - C:/lscc/diamond/3.8/ispfpga/vhdl_packages/standard.vhd(9,9-9,17) (VHDL-1014) analyzing package standard (VHDL-1481) Analyzing VHDL file C:/lscc/diamond/3.8/ispfpga/vhdl_packages/std_1164.vhd INFO - C:/lscc/diamond/3.8/ispfpga/vhdl_packages/std_1164.vhd(15,9-15,23) (VHDL-1014) analyzing package std_logic_1164 INFO - C:/lscc/diamond/3.8/ispfpga/vhdl_packages/std_1164.vhd(178,14-178,28) (VHDL-1013) analyzing package body std_logic_1164 (VHDL-1481) Analyzing VHDL file C:/lscc/diamond/3.8/ispfpga/vhdl_packages/mgc_qsim.vhd INFO - C:/lscc/diamond/3.8/ispfpga/vhdl_packages/mgc_qsim.vhd(18,9-18,19) (VHDL-1014) analyzing package qsim_logic INFO - C:/lscc/diamond/3.8/ispfpga/vhdl_packages/mgc_qsim.vhd(753,14-753,24) (VHDL-1013) analyzing package body qsim_logic (VHDL-1481) Analyzing VHDL file C:/lscc/diamond/3.8/ispfpga/vhdl_packages/numeric_bit.vhd INFO - C:/lscc/diamond/3.8/ispfpga/vhdl_packages/numeric_bit.vhd(54,9-54,20) (VHDL-1014) analyzing package numeric_bit INFO - C:/lscc/diamond/3.8/ispfpga/vhdl_packages/numeric_bit.vhd(834,14-834,25) (VHDL-1013) analyzing package body numeric_bit (VHDL-1481) Analyzing VHDL file C:/lscc/diamond/3.8/ispfpga/vhdl_packages/numeric_std.vhd INFO - C:/lscc/diamond/3.8/ispfpga/vhdl_packages/numeric_std.vhd(57,9-57,20) (VHDL-1014) analyzing package numeric_std INFO - C:/lscc/diamond/3.8/ispfpga/vhdl_packages/numeric_std.vhd(874,14-874,25) (VHDL-1013) analyzing package body numeric_std (VHDL-1481) Analyzing VHDL file C:/lscc/diamond/3.8/ispfpga/vhdl_packages/textio.vhd INFO - C:/lscc/diamond/3.8/ispfpga/vhdl_packages/textio.vhd(13,9-13,15) (VHDL-1014) analyzing package textio INFO - C:/lscc/diamond/3.8/ispfpga/vhdl_packages/textio.vhd(114,14-114,20) (VHDL-1013) analyzing package body textio (VHDL-1481) Analyzing VHDL file C:/lscc/diamond/3.8/ispfpga/vhdl_packages/std_logic_textio.vhd INFO - C:/lscc/diamond/3.8/ispfpga/vhdl_packages/std_logic_textio.vhd(26,9-26,25) (VHDL-1014) analyzing package std_logic_textio INFO - C:/lscc/diamond/3.8/ispfpga/vhdl_packages/std_logic_textio.vhd(72,14-72,30) (VHDL-1013) analyzing package body std_logic_textio (VHDL-1481) Analyzing VHDL file C:/lscc/diamond/3.8/ispfpga/vhdl_packages/syn_attr.vhd INFO - C:/lscc/diamond/3.8/ispfpga/vhdl_packages/syn_attr.vhd(39,9-39,19) (VHDL-1014) analyzing package attributes (VHDL-1481) Analyzing VHDL file C:/lscc/diamond/3.8/ispfpga/vhdl_packages/syn_misc.vhd INFO - C:/lscc/diamond/3.8/ispfpga/vhdl_packages/syn_misc.vhd(30,9-30,23) (VHDL-1014) analyzing package std_logic_misc INFO - C:/lscc/diamond/3.8/ispfpga/vhdl_packages/syn_misc.vhd(182,14-182,28) (VHDL-1013) analyzing package body std_logic_misc INFO - ./.__tmp_vxr_0_(56,9-56,18) (VHDL-1014) analyzing package math_real INFO - ./.__tmp_vxr_0_(685,14-685,23) (VHDL-1013) analyzing package body math_real (VHDL-1481) Analyzing VHDL file C:/lscc/diamond/3.8/ispfpga/vhdl_packages/mixed_lang_vltype.vhd INFO - C:/lscc/diamond/3.8/ispfpga/vhdl_packages/mixed_lang_vltype.vhd(9,9-9,17) (VHDL-1014) analyzing package vl_types INFO - C:/lscc/diamond/3.8/ispfpga/vhdl_packages/mixed_lang_vltype.vhd(88,14-88,22) (VHDL-1013) analyzing package body vl_types (VHDL-1481) Analyzing VHDL file C:/lscc/diamond/3.8/ispfpga/vhdl_packages/syn_arit.vhd INFO - C:/lscc/diamond/3.8/ispfpga/vhdl_packages/syn_arit.vhd(25,9-25,24) (VHDL-1014) analyzing package std_logic_arith INFO - C:/lscc/diamond/3.8/ispfpga/vhdl_packages/syn_arit.vhd(206,14-206,29) (VHDL-1013) analyzing package body std_logic_arith (VHDL-1481) Analyzing VHDL file C:/lscc/diamond/3.8/ispfpga/vhdl_packages/syn_sign.vhd INFO - C:/lscc/diamond/3.8/ispfpga/vhdl_packages/syn_sign.vhd(35,9-35,25) (VHDL-1014) analyzing package std_logic_signed INFO - C:/lscc/diamond/3.8/ispfpga/vhdl_packages/syn_sign.vhd(96,14-96,30) (VHDL-1013) analyzing package body std_logic_signed (VHDL-1481) Analyzing VHDL file C:/lscc/diamond/3.8/ispfpga/vhdl_packages/syn_unsi.vhd INFO - C:/lscc/diamond/3.8/ispfpga/vhdl_packages/syn_unsi.vhd(35,9-35,27) (VHDL-1014) analyzing package std_logic_unsigned INFO - C:/lscc/diamond/3.8/ispfpga/vhdl_packages/syn_unsi.vhd(94,14-94,32) (VHDL-1013) analyzing package body std_logic_unsigned (VHDL-1481) Analyzing VHDL file C:/lscc/diamond/3.8/ispfpga/vhdl_packages/synattr.vhd INFO - C:/lscc/diamond/3.8/ispfpga/vhdl_packages/synattr.vhd(50,9-50,19) (VHDL-1014) analyzing package attributes (VERI-1482) Analyzing Verilog file C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v (VERI-1482) Analyzing Verilog file C:/TFG/exp6/esquema_con_gpio/esquema_con_gpio.v (VERI-1482) Analyzing Verilog file C:/TFG/exp6/dos_gpio/soc/dos_gpio.v INFO - C:/TFG/exp6/dos_gpio/soc/dos_gpio.v(46,10-46,25) (VERI-1328) analyzing included file C:/TFG/exp6/dos_gpio/soc/system_conf.v INFO - C:/TFG/exp6/dos_gpio/soc/dos_gpio.v(327,10-327,59) (VERI-1328) analyzing included file C:/TFG/exp6/dos_gpio/soc/../components/lm8/rtl/verilog/lm8_include_all.v INFO - C:/TFG/exp6/dos_gpio/soc/../components/lm8/rtl/verilog/lm8_include_all.v(48,10-48,21) (VERI-1328) analyzing included file C:/TFG/exp6/dos_gpio/soc/pmi_def.v INFO - C:/TFG/exp6/dos_gpio/soc/../components/lm8/rtl/verilog/lm8_include_all.v(50,10-50,25) (VERI-1328) analyzing included file C:/TFG/exp6/dos_gpio/soc/system_conf.v INFO - C:/TFG/exp6/dos_gpio/soc/../components/lm8/rtl/verilog/lm8_include_all.v(51,10-51,55) (VERI-1328) analyzing included file C:/TFG/exp6/dos_gpio/soc/../components/lm8/rtl/verilog/lm8_include.v INFO - C:/TFG/exp6/dos_gpio/soc/../components/lm8/rtl/verilog/lm8_include_all.v(52,10-52,57) (VERI-1328) analyzing included file C:/TFG/exp6/dos_gpio/soc/../components/lm8/rtl/verilog/lm8_interrupt.v INFO - C:/TFG/exp6/dos_gpio/soc/../components/lm8/rtl/verilog/lm8_interrupt.v(47,10-47,25) (VERI-1328) analyzing included file C:/TFG/exp6/dos_gpio/soc/system_conf.v INFO - C:/TFG/exp6/dos_gpio/soc/../components/lm8/rtl/verilog/lm8_include_all.v(53,10-53,55) (VERI-1328) analyzing included file C:/TFG/exp6/dos_gpio/soc/../components/lm8/rtl/verilog/lm8_io_cntl.v INFO - C:/TFG/exp6/dos_gpio/soc/../components/lm8/rtl/verilog/lm8_include_all.v(54,10-54,57) (VERI-1328) analyzing included file C:/TFG/exp6/dos_gpio/soc/../components/lm8/rtl/verilog/lm8_flow_cntl.v INFO - C:/TFG/exp6/dos_gpio/soc/../components/lm8/rtl/verilog/lm8_include_all.v(55,10-55,52) (VERI-1328) analyzing included file C:/TFG/exp6/dos_gpio/soc/../components/lm8/rtl/verilog/lm8_idec.v INFO - C:/TFG/exp6/dos_gpio/soc/../components/lm8/rtl/verilog/lm8_include_all.v(56,10-56,51) (VERI-1328) analyzing included file C:/TFG/exp6/dos_gpio/soc/../components/lm8/rtl/verilog/lm8_alu.v INFO - C:/TFG/exp6/dos_gpio/soc/../components/lm8/rtl/verilog/lm8_include_all.v(57,10-57,52) (VERI-1328) analyzing included file C:/TFG/exp6/dos_gpio/soc/../components/lm8/rtl/verilog/lm8_core.v WARNING - C:/TFG/exp6/dos_gpio/soc/../components/lm8/rtl/verilog/lm8_core.v(82,4-82,47) (VERI-1199) parameter declaration becomes local in lm8_core with formal parameter declaration list WARNING - C:/TFG/exp6/dos_gpio/soc/../components/lm8/rtl/verilog/lm8_core.v(83,4-83,47) (VERI-1199) parameter declaration becomes local in lm8_core with formal parameter declaration list WARNING - C:/TFG/exp6/dos_gpio/soc/../components/lm8/rtl/verilog/lm8_core.v(84,4-84,47) (VERI-1199) parameter declaration becomes local in lm8_core with formal parameter declaration list INFO - C:/TFG/exp6/dos_gpio/soc/../components/lm8/rtl/verilog/lm8_include_all.v(58,10-58,51) (VERI-1328) analyzing included file C:/TFG/exp6/dos_gpio/soc/../components/lm8/rtl/verilog/lm8_top.v WARNING - C:/TFG/exp6/dos_gpio/soc/../components/lm8/rtl/verilog/lm8_top.v(113,4-113,90) (VERI-1199) parameter declaration becomes local in lm8 with formal parameter declaration list WARNING - C:/TFG/exp6/dos_gpio/soc/../components/lm8/rtl/verilog/lm8_top.v(114,4-114,96) (VERI-1199) parameter declaration becomes local in lm8 with formal parameter declaration list INFO - C:/TFG/exp6/dos_gpio/soc/dos_gpio.v(328,10-328,49) (VERI-1328) analyzing included file C:/TFG/exp6/dos_gpio/soc/../components/gpio/rtl/verilog/gpio.v INFO - C:/TFG/exp6/dos_gpio/soc/../components/gpio/rtl/verilog/gpio.v(79,10-79,25) (VERI-1328) analyzing included file C:/TFG/exp6/dos_gpio/soc/system_conf.v WARNING - C:/TFG/exp6/dos_gpio/soc/../components/gpio/rtl/verilog/gpio.v(176,4-176,23) (VERI-1199) parameter declaration becomes local in gpio with formal parameter declaration list INFO - C:/TFG/exp6/dos_gpio/soc/dos_gpio.v(329,10-329,49) (VERI-1328) analyzing included file C:/TFG/exp6/dos_gpio/soc/../components/gpio/rtl/verilog/tpio.v INFO - C:/TFG/exp6/dos_gpio/soc/../components/gpio/rtl/verilog/tpio.v(65,10-65,25) (VERI-1328) analyzing included file C:/TFG/exp6/dos_gpio/soc/system_conf.v WARNING - C:/TFG/exp6/dos_gpio/soc/../components/gpio/rtl/verilog/tpio.v(87,4-87,23) (VERI-1199) parameter declaration becomes local in tpio with formal parameter declaration list (VHDL-1481) Analyzing VHDL file C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.vhd (VHDL-1481) Analyzing VHDL file C:/TFG/exp6/dos_gpio/soc/dos_gpio_vhd.vhd INFO - C:/TFG/exp6/dos_gpio/soc/dos_gpio_vhd.vhd(4,8-4,20) (VHDL-1012) analyzing entity dos_gpio_vhd INFO - C:/TFG/exp6/dos_gpio/soc/dos_gpio_vhd.vhd(14,14-14,28) (VHDL-1010) analyzing architecture dos_gpio_vhd_a (VHDL-1481) Analyzing VHDL file C:/TFG/exp6/div2.vhd INFO - C:/TFG/exp6/div2.vhd(14,8-14,12) (VHDL-1012) analyzing entity div2 INFO - C:/TFG/exp6/div2.vhd(22,14-22,23) (VHDL-1010) analyzing architecture structure INFO - C:/TFG/exp6/esquema_con_gpio/esquema_con_gpio.v(3,8-3,24) (VERI-1018) compiling module esquema_con_gpio INFO - C:/TFG/exp6/esquema_con_gpio/esquema_con_gpio.v(3,1-59,10) (VERI-9000) elaborating module 'esquema_con_gpio' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(857,1-860,10) (VERI-9000) elaborating module 'OB_uniq_1' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(857,1-860,10) (VERI-9000) elaborating module 'OB_uniq_2' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(857,1-860,10) (VERI-9000) elaborating module 'OB_uniq_3' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(857,1-860,10) (VERI-9000) elaborating module 'OB_uniq_4' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(857,1-860,10) (VERI-9000) elaborating module 'OB_uniq_5' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(857,1-860,10) (VERI-9000) elaborating module 'OB_uniq_6' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(857,1-860,10) (VERI-9000) elaborating module 'OB_uniq_7' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(857,1-860,10) (VERI-9000) elaborating module 'OB_uniq_8' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(857,1-860,10) (VERI-9000) elaborating module 'OB_uniq_9' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(857,1-860,10) (VERI-9000) elaborating module 'OB_uniq_10' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(498,1-501,10) (VERI-9000) elaborating module 'IB_uniq_1' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(498,1-501,10) (VERI-9000) elaborating module 'IB_uniq_2' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(498,1-501,10) (VERI-9000) elaborating module 'IB_uniq_3' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(498,1-501,10) (VERI-9000) elaborating module 'IB_uniq_4' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(498,1-501,10) (VERI-9000) elaborating module 'IB_uniq_5' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(498,1-501,10) (VERI-9000) elaborating module 'IB_uniq_6' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(498,1-501,10) (VERI-9000) elaborating module 'IB_uniq_7' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(498,1-501,10) (VERI-9000) elaborating module 'IB_uniq_8' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(498,1-501,10) (VERI-9000) elaborating module 'IB_uniq_9' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1120,1-1122,10) (VERI-9000) elaborating module 'VHI_uniq_1' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1120,1-1122,10) (VERI-9000) elaborating module 'VHI_uniq_2' INFO - C:/TFG/exp6/esquema_con_gpio/esquema_con_gpio.v(34,1-34,53) (VERI-1231) going to vhdl side to elaborate module div2 INFO - C:/TFG/exp6/div2.vhd(14,8-14,12) (VHDL-1067) elaborating div2_uniq_0(Structure) INFO - C:/TFG/exp6/div2.vhd(60,5-62,27) (VHDL-1399) going to verilog side to elaborate module FD1P3DX INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,8-187,15) (VERI-1018) compiling module FD1P3DX_uniq_1 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_1' INFO - C:/TFG/exp6/div2.vhd(60,5-62,27) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6/div2.vhd(64,5-65,33) (VHDL-1399) going to verilog side to elaborate module VHI INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1120,8-1120,11) (VERI-1018) compiling module VHI_uniq_3 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1120,1-1122,10) (VERI-9000) elaborating module 'VHI_uniq_3' INFO - C:/TFG/exp6/div2.vhd(64,5-65,33) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6/div2.vhd(67,5-70,23) (VHDL-1399) going to verilog side to elaborate module FADD2B INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(138,8-138,14) (VERI-1018) compiling module FADD2B_uniq_1 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(138,1-142,10) (VERI-9000) elaborating module 'FADD2B_uniq_1' INFO - C:/TFG/exp6/div2.vhd(67,5-70,23) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6/div2.vhd(72,5-74,40) (VHDL-1399) going to verilog side to elaborate module CU2 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(129,8-129,11) (VERI-1018) compiling module CU2_uniq_1 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(129,1-136,10) (VERI-9000) elaborating module 'CU2_uniq_1' INFO - C:/TFG/exp6/div2.vhd(72,5-74,40) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6/div2.vhd(76,5-77,33) (VHDL-1399) going to verilog side to elaborate module VLO INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1124,8-1124,11) (VERI-1018) compiling module VLO_uniq_1 INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1124,1-1126,10) (VERI-9000) elaborating module 'VLO_uniq_1' INFO - C:/TFG/exp6/div2.vhd(76,5-77,33) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/TFG/exp6/esquema_con_gpio/esquema_con_gpio.v(34,1-34,53) (VERI-1232) back to verilog to continue elaboration INFO - C:/TFG/exp6/esquema_con_gpio/esquema_con_gpio.v(56,1-57,58) (VERI-1231) going to vhdl side to elaborate module dos_gpio_vhd INFO - C:/TFG/exp6/dos_gpio/soc/dos_gpio_vhd.vhd(4,8-4,20) (VHDL-1067) elaborating dos_gpio_vhd_uniq_0(dos_gpio_vhd_a) INFO - C:/TFG/exp6/dos_gpio/soc/dos_gpio_vhd.vhd(28,1-35,6) (VHDL-1399) going to verilog side to elaborate module dos_gpio INFO - C:/TFG/exp6/dos_gpio/soc/dos_gpio.v(332,8-332,16) (VERI-1018) compiling module dos_gpio_uniq_1 INFO - C:/TFG/exp6/dos_gpio/soc/dos_gpio.v(332,1-679,10) (VERI-9000) elaborating module 'dos_gpio_uniq_1' INFO - C:/TFG/exp6/dos_gpio/soc/dos_gpio.v(48,1-325,10) (VERI-9000) elaborating module 'arbiter2_uniq_1' INFO - C:/TFG/exp6/dos_gpio/soc/../components/lm8/rtl/verilog/lm8_top.v(50,1-1126,10) (VERI-9000) elaborating module 'lm8_uniq_1' INFO - C:/TFG/exp6/dos_gpio/soc/../components/gpio/rtl/verilog/gpio.v(80,1-1887,10) (VERI-9000) elaborating module 'gpio_uniq_1' INFO - C:/TFG/exp6/dos_gpio/soc/../components/gpio/rtl/verilog/gpio.v(80,1-1887,10) (VERI-9000) elaborating module 'gpio_uniq_2' INFO - C:/TFG/exp6/dos_gpio/soc/../components/gpio/rtl/verilog/gpio.v(80,1-1887,10) (VERI-9000) elaborating module 'gpio_uniq_3' INFO - C:/TFG/exp6/dos_gpio/soc/../components/lm8/rtl/verilog/lm8_core.v(47,1-661,10) (VERI-9000) elaborating module 'lm8_core_uniq_1' INFO - C:/TFG/exp6/dos_gpio/soc/../components/lm8/rtl/verilog/lm8_idec.v(47,1-283,10) (VERI-9000) elaborating module 'lm8_idec_uniq_1' INFO - C:/TFG/exp6/dos_gpio/soc/../components/lm8/rtl/verilog/lm8_alu.v(47,1-137,10) (VERI-9000) elaborating module 'lm8_alu_uniq_1' INFO - C:/TFG/exp6/dos_gpio/soc/../components/lm8/rtl/verilog/lm8_flow_cntl.v(49,1-534,10) (VERI-9000) elaborating module 'lm8_flow_cntl_uniq_1' INFO - C:/TFG/exp6/dos_gpio/soc/../components/lm8/rtl/verilog/lm8_io_cntl.v(47,1-131,10) (VERI-9000) elaborating module 'lm8_io_cntl_uniq_1' INFO - C:/TFG/exp6/dos_gpio/soc/../components/lm8/rtl/verilog/lm8_interrupt.v(49,1-136,10) (VERI-9000) elaborating module 'lm8_interrupt_uniq_1' INFO - C:/TFG/exp6/dos_gpio/soc/dos_gpio.v(332,1-679,10) (VERI-9000) elaborating module 'dos_gpio_uniq_1' INFO - C:/TFG/exp6/dos_gpio/soc/dos_gpio.v(48,1-325,10) (VERI-9000) elaborating module 'arbiter2_uniq_1' INFO - C:/TFG/exp6/dos_gpio/soc/../components/lm8/rtl/verilog/lm8_top.v(50,1-1126,10) (VERI-9000) elaborating module 'lm8_uniq_1' INFO - C:/TFG/exp6/dos_gpio/soc/../components/gpio/rtl/verilog/gpio.v(80,1-1887,10) (VERI-9000) elaborating module 'gpio_uniq_1' INFO - C:/TFG/exp6/dos_gpio/soc/../components/gpio/rtl/verilog/gpio.v(80,1-1887,10) (VERI-9000) elaborating module 'gpio_uniq_2' INFO - C:/TFG/exp6/dos_gpio/soc/../components/gpio/rtl/verilog/gpio.v(80,1-1887,10) (VERI-9000) elaborating module 'gpio_uniq_3' INFO - C:/TFG/exp6/dos_gpio/soc/../components/lm8/rtl/verilog/lm8_core.v(47,1-661,10) (VERI-9000) elaborating module 'lm8_core_uniq_1' INFO - C:/TFG/exp6/dos_gpio/soc/../components/gpio/rtl/verilog/tpio.v(66,1-189,10) (VERI-9000) elaborating module 'tpio_uniq_1' INFO - C:/TFG/exp6/dos_gpio/soc/../components/gpio/rtl/verilog/tpio.v(66,1-189,10) (VERI-9000) elaborating module 'tpio_uniq_2' INFO - C:/TFG/exp6/dos_gpio/soc/../components/gpio/rtl/verilog/tpio.v(66,1-189,10) (VERI-9000) elaborating module 'tpio_uniq_3' INFO - C:/TFG/exp6/dos_gpio/soc/../components/gpio/rtl/verilog/tpio.v(66,1-189,10) (VERI-9000) elaborating module 'tpio_uniq_4' INFO - C:/TFG/exp6/dos_gpio/soc/../components/gpio/rtl/verilog/tpio.v(66,1-189,10) (VERI-9000) elaborating module 'tpio_uniq_5' INFO - C:/TFG/exp6/dos_gpio/soc/../components/gpio/rtl/verilog/tpio.v(66,1-189,10) (VERI-9000) elaborating module 'tpio_uniq_6' INFO - C:/TFG/exp6/dos_gpio/soc/../components/gpio/rtl/verilog/tpio.v(66,1-189,10) (VERI-9000) elaborating module 'tpio_uniq_7' INFO - C:/TFG/exp6/dos_gpio/soc/../components/gpio/rtl/verilog/tpio.v(66,1-189,10) (VERI-9000) elaborating module 'tpio_uniq_8' INFO - C:/TFG/exp6/dos_gpio/soc/../components/gpio/rtl/verilog/tpio.v(66,1-189,10) (VERI-9000) elaborating module 'tpio_uniq_9' INFO - C:/TFG/exp6/dos_gpio/soc/../components/gpio/rtl/verilog/tpio.v(66,1-189,10) (VERI-9000) elaborating module 'tpio_uniq_10' INFO - C:/TFG/exp6/dos_gpio/soc/../components/gpio/rtl/verilog/tpio.v(66,1-189,10) (VERI-9000) elaborating module 'tpio_uniq_11' INFO - C:/TFG/exp6/dos_gpio/soc/../components/gpio/rtl/verilog/tpio.v(66,1-189,10) (VERI-9000) elaborating module 'tpio_uniq_12' INFO - C:/TFG/exp6/dos_gpio/soc/../components/gpio/rtl/verilog/tpio.v(66,1-189,10) (VERI-9000) elaborating module 'tpio_uniq_13' INFO - C:/TFG/exp6/dos_gpio/soc/../components/gpio/rtl/verilog/tpio.v(66,1-189,10) (VERI-9000) elaborating module 'tpio_uniq_14' INFO - C:/TFG/exp6/dos_gpio/soc/../components/gpio/rtl/verilog/tpio.v(66,1-189,10) (VERI-9000) elaborating module 'tpio_uniq_15' INFO - C:/TFG/exp6/dos_gpio/soc/../components/gpio/rtl/verilog/tpio.v(66,1-189,10) (VERI-9000) elaborating module 'tpio_uniq_16' INFO - C:/TFG/exp6/dos_gpio/soc/../components/gpio/rtl/verilog/tpio.v(66,1-189,10) (VERI-9000) elaborating module 'tpio_uniq_17' INFO - C:/TFG/exp6/dos_gpio/soc/../components/gpio/rtl/verilog/tpio.v(66,1-189,10) (VERI-9000) elaborating module 'tpio_uniq_18' INFO - C:/TFG/exp6/dos_gpio/soc/../components/gpio/rtl/verilog/tpio.v(66,1-189,10) (VERI-9000) elaborating module 'tpio_uniq_19' INFO - C:/TFG/exp6/dos_gpio/soc/../components/gpio/rtl/verilog/tpio.v(66,1-189,10) (VERI-9000) elaborating module 'tpio_uniq_20' INFO - C:/TFG/exp6/dos_gpio/soc/../components/gpio/rtl/verilog/tpio.v(66,1-189,10) (VERI-9000) elaborating module 'tpio_uniq_21' INFO - C:/TFG/exp6/dos_gpio/soc/../components/gpio/rtl/verilog/tpio.v(66,1-189,10) (VERI-9000) elaborating module 'tpio_uniq_22' INFO - C:/TFG/exp6/dos_gpio/soc/../components/gpio/rtl/verilog/tpio.v(66,1-189,10) (VERI-9000) elaborating module 'tpio_uniq_23' INFO - C:/TFG/exp6/dos_gpio/soc/../components/gpio/rtl/verilog/tpio.v(66,1-189,10) (VERI-9000) elaborating module 'tpio_uniq_24' INFO - C:/TFG/exp6/dos_gpio/soc/../components/gpio/rtl/verilog/tpio.v(66,1-189,10) (VERI-9000) elaborating module 'tpio_uniq_25' INFO - C:/TFG/exp6/dos_gpio/soc/../components/gpio/rtl/verilog/tpio.v(66,1-189,10) (VERI-9000) elaborating module 'tpio_uniq_26' INFO - C:/TFG/exp6/dos_gpio/soc/../components/gpio/rtl/verilog/tpio.v(66,1-189,10) (VERI-9000) elaborating module 'tpio_uniq_27' INFO - C:/TFG/exp6/dos_gpio/soc/../components/gpio/rtl/verilog/tpio.v(66,1-189,10) (VERI-9000) elaborating module 'tpio_uniq_28' INFO - C:/TFG/exp6/dos_gpio/soc/../components/lm8/rtl/verilog/lm8_idec.v(47,1-283,10) (VERI-9000) elaborating module 'lm8_idec_uniq_1' INFO - C:/TFG/exp6/dos_gpio/soc/../components/lm8/rtl/verilog/lm8_alu.v(47,1-137,10) (VERI-9000) elaborating module 'lm8_alu_uniq_1' INFO - C:/TFG/exp6/dos_gpio/soc/../components/lm8/rtl/verilog/lm8_flow_cntl.v(49,1-534,10) (VERI-9000) elaborating module 'lm8_flow_cntl_uniq_1' INFO - C:/TFG/exp6/dos_gpio/soc/../components/lm8/rtl/verilog/lm8_io_cntl.v(47,1-131,10) (VERI-9000) elaborating module 'lm8_io_cntl_uniq_1' INFO - C:/TFG/exp6/dos_gpio/soc/../components/lm8/rtl/verilog/lm8_interrupt.v(49,1-136,10) (VERI-9000) elaborating module 'lm8_interrupt_uniq_1' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(82,1-87,10) (VERI-9000) elaborating module 'BB_uniq_1' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(82,1-87,10) (VERI-9000) elaborating module 'BB_uniq_2' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(82,1-87,10) (VERI-9000) elaborating module 'BB_uniq_3' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(82,1-87,10) (VERI-9000) elaborating module 'BB_uniq_4' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(82,1-87,10) (VERI-9000) elaborating module 'BB_uniq_5' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(82,1-87,10) (VERI-9000) elaborating module 'BB_uniq_6' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(82,1-87,10) (VERI-9000) elaborating module 'BB_uniq_7' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(82,1-87,10) (VERI-9000) elaborating module 'BB_uniq_8' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(82,1-87,10) (VERI-9000) elaborating module 'BB_uniq_9' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(82,1-87,10) (VERI-9000) elaborating module 'BB_uniq_10' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(82,1-87,10) (VERI-9000) elaborating module 'BB_uniq_11' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(82,1-87,10) (VERI-9000) elaborating module 'BB_uniq_12' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(82,1-87,10) (VERI-9000) elaborating module 'BB_uniq_13' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(82,1-87,10) (VERI-9000) elaborating module 'BB_uniq_14' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(82,1-87,10) (VERI-9000) elaborating module 'BB_uniq_15' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(82,1-87,10) (VERI-9000) elaborating module 'BB_uniq_16' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(82,1-87,10) (VERI-9000) elaborating module 'BB_uniq_17' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(82,1-87,10) (VERI-9000) elaborating module 'BB_uniq_18' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(82,1-87,10) (VERI-9000) elaborating module 'BB_uniq_19' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(82,1-87,10) (VERI-9000) elaborating module 'BB_uniq_20' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(82,1-87,10) (VERI-9000) elaborating module 'BB_uniq_21' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(82,1-87,10) (VERI-9000) elaborating module 'BB_uniq_22' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(82,1-87,10) (VERI-9000) elaborating module 'BB_uniq_23' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(82,1-87,10) (VERI-9000) elaborating module 'BB_uniq_24' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(82,1-87,10) (VERI-9000) elaborating module 'BB_uniq_25' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(82,1-87,10) (VERI-9000) elaborating module 'BB_uniq_26' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(82,1-87,10) (VERI-9000) elaborating module 'BB_uniq_27' INFO - C:/lscc/diamond/3.8/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(82,1-87,10) (VERI-9000) elaborating module 'BB_uniq_28' INFO - C:/TFG/exp6/dos_gpio/soc/dos_gpio_vhd.vhd(28,1-35,6) (VHDL-1400) back to vhdl to continue elaboration WARNING - C:/TFG/exp6/esquema_con_gpio/esquema_con_gpio.v(56,14-57,57) (VERI-1397) size mismatch in mixed language port association, vhdl port gpioentpio_in INFO - C:/TFG/exp6/esquema_con_gpio/esquema_con_gpio.v(56,1-57,58) (VERI-1232) back to verilog to continue elaboration WARNING - C:/TFG/exp6/dos_gpio/soc/dos_gpio.v(553,1-586,35) (VERI-1927) port PIO_BOTH_IN remains unconnected for this instance WARNING - C:/TFG/exp6/dos_gpio/soc/dos_gpio.v(594,1-627,35) (VERI-1927) port PIO_IN remains unconnected for this instance WARNING - C:/TFG/exp6/dos_gpio/soc/dos_gpio.v(635,1-668,35) (VERI-1927) port PIO_BOTH_IN remains unconnected for this instance Done: design load finished with (0) errors, and (11) warnings