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dc.contributor.authorGarcía Yágüez, Álvaro
dc.contributor.authorLlanos Ferraris, Diego Rafael 
dc.contributor.authorGonzález Escribano, Arturo 
dc.date.accessioned2024-10-04T14:37:24Z
dc.date.available2024-10-04T14:37:24Z
dc.date.issued2014
dc.identifier.citationIEEE Transactions on Computers, Vol. 63, no. 7, July 2014, pags. 1826-1839, ISSN 0018-9340es
dc.identifier.issn0018-9340es
dc.identifier.urihttps://uvadoc.uva.es/handle/10324/70432
dc.descriptionProducción Científicaes
dc.description.abstractSpeculative parallelization is a runtime technique that optimistically executes sequential code in parallel, checking that no dependence violations arise. In the case of a dependence violation, all mechanisms proposed so far either switch to sequential execution, or conservatively stop and restart the offending thread and all its successors, potentially discarding work that does not depend on this particular violation. In this work we systematically explore the design space of solutions for this problem, proposing a new mechanism that reduces the number of threads that should be restarted when a data dependence violation is found. Our new solution, called exclusive squashing, keeps track of inter-thread dependencies at runtime, selectively stopping and restarting offending threads, together with all threads that have consumed data from them. We have compared this new approach with existent solutions on a real system, executing different applications with loops that are not analyzable at compile time and present as much as 10% of inter-thread dependence violations at runtime. Our experimental results show a relative performance improvement of up to 14%, together with a reduction of one-third of the numbers of squashed threads. The speculative parallelization scheme and benchmarks described in this paper are available under request.es
dc.format.mimetypeapplication/pdfes
dc.language.isoenges
dc.publisherIEEEes
dc.rights.accessRightsinfo:eu-repo/semantics/openAccesses
dc.subjectInformáticaes
dc.subject.classificationThread-level speculationes
dc.subject.classificationOptimistic parallelizationes
dc.subject.classificationloop-based parallelizationes
dc.titleSquashing Alternatives for Software-Based Speculative Parallelizationes
dc.typeinfo:eu-repo/semantics/articlees
dc.identifier.doi10.1109/TC.2013.46es
dc.relation.publisherversionhttps://ieeexplore.ieee.org/document/6475131/es
dc.identifier.publicationfirstpage1826es
dc.identifier.publicationissue7es
dc.identifier.publicationlastpage1839es
dc.identifier.publicationtitleIEEE Transactions on Computerses
dc.identifier.publicationvolume63es
dc.peerreviewedSIes
dc.description.projectThe authors would like to thank the anonymous referees for their valuable suggestions, and Dr. Marcelo Cintra and Dr. Belén Palop for many helpful discussions on this topic. This research is partly supported by the Spanish Government (TIN2007-62302, TSI-020302-2008-89, CENIT OCEANLIDER), the CAPAP-H network (TIN2010-12011-E, TIN2011-15734-E), and Junta de Castilla y León, Spain (VA172A12-2). Part of this work was carried out under the HPC-EUROPA2 project (project number: 228398), with the support of the European Community, Research Infrastructure Action of the FP7.es
dc.identifier.essn1557-9956es
dc.identifier.essn2326-3814es
dc.type.hasVersioninfo:eu-repo/semantics/publishedVersiones
dc.subject.unesco1203 Ciencia de Los Ordenadoreses
dc.subject.unesco3304 Tecnología de Los Ordenadoreses


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