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dc.contributor.authorCintra, M.
dc.contributor.authorLlanos Ferraris, Diego Rafael 
dc.date.accessioned2024-10-04T15:36:25Z
dc.date.available2024-10-04T15:36:25Z
dc.date.issued2005
dc.identifier.citationIEEE Transactions on Parallel and Distributed Systems, vol. 16, no. 6, pags. 562-576, June 2005.es
dc.identifier.issn1045-9219es
dc.identifier.urihttps://uvadoc.uva.es/handle/10324/70442
dc.descriptionProducción Científicaes
dc.description.abstractWith speculative parallelization, code sections that cannot be fully analyzed by the compiler are optimistically executed in parallel. Hardware schemes are fast but expensive and require modifications to the processors and/or memory system. Software schemes require no changes to the hardware of existing shared-memory systems, but can suffer from significant overheads involved with the speculative execution. In fact, the performance of software schemes is highly dependent on application characteristics, the design and implementation of the scheme, and the system configuration and size. This paper explores the design space of a recently proposed software speculative parallelization scheme. In the process, we gain insight into the most beneficial features of software schemes for speculative parallelization, as well as the most influential application characteristics. For instance, experimental results show that, contrary to intuition, checking for data dependence violations on every speculative store, as opposed to at commit time, leads to little performance degradation in the worst case and to significantly better performance with large configurations. Also, scheduling policies based on windows can perform very close to fully dynamic policies with a fraction of the memory overhead. Finally, experimental results show consistent speedups in the execution of loops that cannot be parallelized at compile time, both with and without RAW data dependences, for 4 to 32 processors.es
dc.format.mimetypeapplication/pdfes
dc.language.isoenges
dc.publisherIEEE Presses
dc.rights.accessRightsinfo:eu-repo/semantics/openAccesses
dc.subjectInformáticaes
dc.subject.classificationSpeculative parallelizationes
dc.subject.classificationThread-level speculationes
dc.subject.classificationParallel architectureses
dc.titleDesign space exploration of a software speculative parallelization schemees
dc.typeinfo:eu-repo/semantics/articlees
dc.identifier.doi10.1109/TPDS.2005.69es
dc.relation.publisherversionhttps://ieeexplore.ieee.org/document/1425444/es
dc.identifier.publicationfirstpage562es
dc.identifier.publicationissue6es
dc.identifier.publicationlastpage576es
dc.identifier.publicationtitleIEEE Transactions on Parallel and Distributed Systemses
dc.identifier.publicationvolume16es
dc.peerreviewedSIes
dc.description.projectThis work was supported in part by the European Commission under grants HPRI-CT-1999-00026 and RII3-CT-2003-506079, and by EPSRC under grant GR/R65169/01.es
dc.type.hasVersioninfo:eu-repo/semantics/publishedVersiones
dc.subject.unesco1203 Ciencia de Los Ordenadoreses
dc.subject.unesco3304 Tecnología de Los Ordenadoreses


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