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<dc:title>Admittance memory cycles of Ta2O5-ZrO2-based RRAM devices</dc:title>
<dc:creator>Dueñas Carazo, Salvador</dc:creator>
<dc:creator>Castán Lanaspa, María Helena</dc:creator>
<dc:creator>González Ossorio, Óscar</dc:creator>
<dc:creator>Domínguez, Leidy Azucena</dc:creator>
<dc:creator>García García, Héctor</dc:creator>
<dc:creator>Kalam, Kristjan</dc:creator>
<dc:creator>Kukli, Kaupo</dc:creator>
<dc:creator>Ritala, Mikko</dc:creator>
<dc:creator>Leskelä, Markku</dc:creator>
<dc:description>Producción Científica</dc:description>
<dc:description>The resistive switching behavior of Ta 2 O 5 -ZrO 2 -based metal-insulator-metal devices was studied. Asymmetrical and repetitive current-voltage loops were observed. Excellent control of admittance parameters in the intermediate states between the high and low resistance ones was achieved, demonstrating suitability to analog and neuromorphic applications. Admittance memory cycles provide relevant information about the switching mechanism, in which the existence of two different metallic species in the dielectric seems to play an important role.</dc:description>
<dc:date>2021-01-08T13:23:27Z</dc:date>
<dc:date>2021-01-08T13:23:27Z</dc:date>
<dc:date>2017</dc:date>
<dc:type>info:eu-repo/semantics/conferenceObject</dc:type>
<dc:identifier>2017 32nd Conference on Design of Circuits and Integrated Systems (DCIS). Barcelona: IEE Xplore, 2017, 4 p.</dc:identifier>
<dc:identifier>978-1-5386-5108-7</dc:identifier>
<dc:identifier>http://uvadoc.uva.es/handle/10324/44667</dc:identifier>
<dc:identifier>10.1109/DCIS.2017.8311627</dc:identifier>
<dc:language>eng</dc:language>
<dc:relation>https://ieeexplore.ieee.org/document/8311627</dc:relation>
<dc:rights>info:eu-repo/semantics/openAccess</dc:rights>
<dc:rights>http://creativecommons.org/licenses/by-nc-nd/4.0/</dc:rights>
<dc:rights>© 2017 IEE Xplore</dc:rights>
<dc:rights>Attribution-NonCommercial-NoDerivatives 4.0 Internacional</dc:rights>
<dc:publisher>IEEE Xplore</dc:publisher>
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