2026-05-05T19:49:39Zhttps://uvadoc.uva.es/oai/requestoai:uvadoc.uva.es:10324/454272021-05-21T22:18:00Zcom_10324_43510com_10324_954com_10324_894col_10324_43515
UVaDOC
author
González Ossorio, Óscar
author
Pérez, Eduardo
author
Dueñas Carazo, Salvador
author
Castán Lanaspa, María Helena
author
García García, Héctor
author
Wenger, Christian
2021-03-02T08:21:59Z
2021-03-02T08:21:59Z
2019
2019 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS). Grenoble, France: IEEE, 2019
978-1-7281-1658-7
http://uvadoc.uva.es/handle/10324/45427
10.1109/EUROSOI-ULIS45800.2019.9041880
The reduction of the pulse width used during the programming of RRAM devices is crucial in order to accomplish fast low-power switching operations. In this work, several pulse width values between 10 μs and 50 ns were evaluated by using the incremental step pulse with verify algorithm (ISPVA) on Al-doped HfO 2 4 kbit RRAM arrays. 1k endurance cycles were performed to assess the switching stability, which showed a remarkable good behavior regardless the pulse width considered. Only the voltages required to perform the switching were impacted by the change of the pulse width. Nevertheless, the voltages needed for each pulse width remain stable along the 1k reset/set cycles. Finally, the data retention, after the endurance test, was evaluated at 150°C for 100 hours. Only a extremely slight increase on the degradation rate of 1 μA after 100 hours was reported between samples programmed by using pulse widths of 10 μs and 50 ns.
eng
Attribution-NonCommercial-NoDerivatives 4.0 Internacional
Resistive RAM memory (RRAM)
Memoria RAM resistiva (RRAM)
Programming algorithm
Algoritmo de programación
Pulse width
Ancho de pulsos
Effective reduction of the programing pulse width in Al: HfO2-based RRAM arrays
info:eu-repo/semantics/conferenceObject