RT info:eu-repo/semantics/article
T1 Using the Xeon Phi platform to run speculatively-parallelized codes
A1 Estébanez, Alvaro
A1 Llanos Ferraris, Diego Rafael
A1 González Escribano, Arturo
AB Intel Xeon Phi accelerators are one of the newest devices used in the field of parallel computing. However, there are comparatively few studies concerning their performance when using most of the existing parallelization techniques. One of them is thread-level speculation, a technique that optimistically tries to extract parallelism of loops without the need of a compile-time analysis that guarantees that the loop can be executed in parallel. In this article we evaluate the performance delivered by an Intel Xeon Phi coprocessor when using a software, state-of-the-art thread-level speculative parallelization library in the execution of well-known benchmarks. We describe both the internal characteristics of the Xeon Phi platform and the particularities of the thread-level speculation library being used as benchmark. Our results show that, although the Xeon Phi delivers a relatively good speedup in comparison with a shared-memory architecture in terms of scalability, the relatively low computing power of its computational units when specific vectorization and SIMD instructions are not fully exploited makes this first generation of Xeon Phi architectures not competitive (in terms of absolute performance) with respect to conventional multicore systems for the execution of speculatively parallelized code.
PB Springer
YR 2017
FD 2017
LK http://uvadoc.uva.es/handle/10324/29110
UL http://uvadoc.uva.es/handle/10324/29110
LA eng
NO International Journal of Parallel Programming, 45(2), 225-214, April 2017, ISSN 0885-7458
NO Producción Científica
DS UVaDOC
RD 24-nov-2024