RT info:eu-repo/semantics/article
T1 Reliability of Logic-in-Memory Circuits in Resistive Memory Arrays
A1 Zanotti, Tommaso
A1 Zambelli, Cristian
A1 Puglisi, Francesco Maria
A1 Milo, Valerio
A1 Pérez Díez, Eduardo
A1 Mahadevaiah, Mamathamba K.
A1 González Ossorio, Óscar
A1 Wenger, Christian
A1 Pavan, Paolo
A1 Olivo, Piero
A1 Ielmini, Daniele
K1 Memoria RAM resistiva (RRAM)
K1 Resistive RAM memory (RRAM)
AB Logic-in-memory (LiM) circuits based on resistive random access memory (RRAM) devices and the material implication logic are promising candidates for the development of low-power computing devices that could fulfill the growing demand of distributed computing systems. However, these circuits are affected by many reliability challenges that arise from device nonidealities (e.g., variability) and the characteristics of the employed circuit architecture. Thus, an accurate investigation of the variability at the array level is needed to evaluate the reliability and performance of such circuit architectures. In this work, we explore the reliability and performance of smart IMPLY (SIMPLY) (i.e., a recently proposed LiM architecture with improved reliability and performance) on two 4-kb RRAM arrays based on different resistive switching oxides integrated in the back end of line (BEOL) of the 0.25-μm BiCMOS process. We analyze the tradeoff between reliability and energy consumption of SIMPLY architecture by exploiting the results of an extensive array-level variability characterization of the two technologies. Finally, we study the worst case performance of a full adder implemented with the SIMPLY architecture and benchmark it on the analogous CMOS implementation.
PB Institute of Electrical and Electronics Engineers
SN 0018-9383
YR 2020
FD 2020
LK http://uvadoc.uva.es/handle/10324/45369
UL http://uvadoc.uva.es/handle/10324/45369
LA eng
NO IEEE Transactions on Electron Devices, 2020, Volume 67, Issue: 11
NO Producción Científica
DS UVaDOC
RD 22-nov-2024