RT info:eu-repo/semantics/conferenceObject
T1 Effective reduction of the programing pulse width in Al: HfO2-based RRAM arrays
A1 González Ossorio, Óscar
A1 Pérez, Eduardo
A1 Dueñas Carazo, Salvador
A1 Castán Lanaspa, María Helena
A1 García García, Héctor
A1 Wenger, Christian
K1 Resistive RAM memory (RRAM)
K1 Memoria RAM resistiva (RRAM)
K1 Programming algorithm
K1 Algoritmo de programación
K1 Pulse width
K1 Ancho de pulsos
AB The reduction of the pulse width used during the programming of RRAM devices is crucial in order to accomplish fast low-power switching operations. In this work, several pulse width values between 10 μs and 50 ns were evaluated by using the incremental step pulse with verify algorithm (ISPVA) on Al-doped HfO 2 4 kbit RRAM arrays. 1k endurance cycles were performed to assess the switching stability, which showed a remarkable good behavior regardless the pulse width considered. Only the voltages required to perform the switching were impacted by the change of the pulse width. Nevertheless, the voltages needed for each pulse width remain stable along the 1k reset/set cycles. Finally, the data retention, after the endurance test, was evaluated at 150°C for 100 hours. Only a extremely slight increase on the degradation rate of 1 μA after 100 hours was reported between samples programmed by using pulse widths of 10 μs and 50 ns.
PB IEEE Xplore
SN 978-1-7281-1658-7
YR 2019
FD 2019
LK http://uvadoc.uva.es/handle/10324/45427
UL http://uvadoc.uva.es/handle/10324/45427
LA eng
NO 2019 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS). Grenoble, France: IEEE, 2019
NO Producción Científica
DS UVaDOC
RD 24-nov-2024