RT info:eu-repo/semantics/article
T1 Energy efficient HPC network topologies with on/off links
A1 Andújar Muñoz, Francisco José
A1 Coll, Salvador
A1 Alonso, Marina
A1 Martínez Rubio, Juan Miguel
A1 López, Pedro
A1 Sánchez, José Luis
A1 Alfaro Cortés, Francisco José
K1 Interconnection networks
K1 Redes de interconexión
K1 1203.17 Informática
AB Energy efficiency is a must in today HPC systems. To achieve this goal, a holistic design based on the use of power-aware components should be performed. One of the key components of an HPC system is the high-speed interconnect. In this paper, we compare and evaluate several design options for the interconnection network of an HPC system, including torus, fat-trees and dragonflies. State of the art low power modes are also used in the interconnection networks. The paper does not only consider energy efficiency at the interconnection network level but also at the system as a whole.The analysis is performed by using a simple yet realistic power model of the system. The model has been adjusted using actual power consumption values measured on a real system. Using this model, realistic multi-job trace-based workloads have been used, obtaining the execution time and energy consumed. The results are presented to ease choosing a system, depending on which parameter, performance or energy consumption, receives the most importance.
PB Elsevier
SN 0167-739X
YR 2022
FD 2022
LK https://uvadoc.uva.es/handle/10324/55695
UL https://uvadoc.uva.es/handle/10324/55695
LA eng
NO Future Generation Computer Systems, 2022, vol. 139, p. 126-138
NO Producción Científica
DS UVaDOC
RD 14-oct-2024