RT info:eu-repo/semantics/conferenceObject
T1 Optimized programming algorithms for multilevel RRAM in hardware neural networks
A1 Milo, V.
A1 Anzalone, F.
A1 Zambelli, C.
A1 Pérez, E.
A1 Mahadevaiah, M.K.
A1 González Ossorio, Óscar
A1 Olivo, P.
A1 Wenger, Christian
A1 Ielmini, D.
K1 Resistive-switching random access memory (RRAM)
K1 Multilevel programming
K1 Resistance variability
K1 Weight quantization
K1 Hardware neural networks
K1 In-memory computing
AB A key requirement for RRAM in neural network accelerators with a large number of synaptic parameters is the multilevel programming. This is hindered by resistance imprecision due to cycle-to-cycle and device-to-device variations. Here, we compare two multilevel programming algorithms to minimize resistance variations in a 4-kbit array of HfO 2 RRAM. We show that gate-based algorithms have the highest reliability. The optimized scheme is used to implement a neural network with 9-level weights, achieving 91.5% (vs. software 93.27%) in MNIST recognition.
PB Institute of Electrical and Electronics Engineers
SN 978-1-7281-6893-7
YR 2021
FD 2021
LK https://uvadoc.uva.es/handle/10324/66068
UL https://uvadoc.uva.es/handle/10324/66068
LA eng
NO 2021 IEEE International Reliability Physics Symposium (IRPS), Monterey, CA, USA, 2021, p. 1-6
NO Producción Científica
DS UVaDOC
RD 24-nov-2024