RT info:eu-repo/semantics/article
T1 Off-chip prefetching based on Hidden Markov Model for non-volatile memory architectures
A1 Lamela, Adrián
A1 Ossorio, Óscar G.
A1 Vinuesa, Guillermo
A1 Sahelices, Benjamín
AB Non-volatile memory technology is now available in commodity hardware. This technology can be used as a backup memory for an external dram cache memory without needing to modify the software. However, the higher read and write latencies of non-volatile memory may exacerbate the memory wall problem. In this work we present a novel off-chip prefetch technique based on a Hidden Markov Model that specifically deals with the latency problem caused by complexity of off-chip memory access patterns. Firstly, we present a thorough analysis of off-chip memory access patterns to identify its complexity in multicore processors. Based on this study, we propose a prefetching module located in the llc which uses two small tables, and where the computational complexity of which is linear with the number of computing threads. Our Markov-based technique is able to keep track and make clustering of several simultaneous groups of memory accesses coming from multiple simultaneous threads in a multicore processor. It can quickly identify complex address groups and trigger prefetch with very high accuracy. Our simulations show an improvement of up to 76% in the hit ratio of an off-chip dram cache for multicore architecture over the conventional prefetch technique (g/dc). Also, the overhead of prefetch requests (failed prefetches) is reduced by 48% in single core simulations and by 83% in multicore simulations.
PB Public Library of Science
YR 2021
FD 2021
LK https://uvadoc.uva.es/handle/10324/66173
UL https://uvadoc.uva.es/handle/10324/66173
LA eng
NO PLOS ONE, 2021, Vol. 16, n.9, p.1-23
NO Producción Científica
DS UVaDOC
RD 08-ago-2024