RT info:eu-repo/semantics/preprint
T1 Challenging Portability Paradigms: FPGA Acceleration Using SYCL and OpenCL
A1 de Castro, Manuel
A1 Andújar, Francisco J.
A1 Osorio, Roberto R.
A1 Carratalá-Sáez, Rocío
A1 Llanos, Diego R.
A2 Universidad de ValladolidDepartamento de Informática
K1 Informática
K1 DataParallelism, FPGA, OpenCL,Portability, SYCL.
K1 1203 Ciencia de Los Ordenadores
K1 3304 Tecnología de Los Ordenadores
AB As the interest in FPGA-based accelerators for HPC applications increases, new challenges also arise, especially concerning different programming and portability issues. This paper aims to provide a snapshot of the current state of the FPGA tooling and its problems. To do so, we evaluate the performance portability of two frameworks for developing FPGA solutions for HPC (SYCL and OpenCL) when using them to port a highly-parallel application to FPGAs, using both ND-range and single-task type of kernels.The developer’s general recommendation when using FPGAs is to develop single-task kernels for them, as they are commonly regarded as more suited for such hardware. However, we discovered that, when using high-level approaches such as OpenCL and SYCL to program a highly-parallel application with no FPGA-tailored optimizations, NDrange kernels significantly outperform single-task codes. Specifically, while SYCL struggles to produce efficient FPGA implementations of applications described as single-task codes, its performance excels with ND-range kernels, a result that was unexpectedly favorable.
YR 2024
FD 2024
LK https://uvadoc.uva.es/handle/10324/69757
UL https://uvadoc.uva.es/handle/10324/69757
LA spa
NO Producción Científica
NO Departamento de Informática
DS UVaDOC
RD 22-dic-2024