RT info:eu-repo/semantics/preprint
T1 Finite-time lyapunov exponent calculation on FPGA using high-level synthesis tools
A1 Castro Caballero, Manuel De
A1 Osorio, Roberto R.
A1 Andújar Muñoz, Francisco José
A1 Carratalá Sáez, Rocío
A1 Torres de la Sierra, Yuri
A1 Llanos Ferraris, Diego Rafael
A2 Universidad de ValladolidDepartamento de Informática
K1 Informática
K1 Data Parallelism · FPGA · HLS · Fluid Dynamics
K1 1203
K1 3304
AB As Field Programmable Gate Arrays (FPGAs) computing capabilities continue to grow, also does the interest on building scientific accelerators around them. Tools like Xilinx’s High-Level Synthesis (HLS) help to bridge the gap between traditional high-level languages such as C and C++, and low-level hardware description languages such as VHDL and Verilog. In this report, we study the implementation of a fluid dynamics application, the Finite-Time Lyapunov Exponent (FTLE) calculation, on FPGA using HLS. We provide speed and resource-consumption results for 2- and 3-dimensional cases.
YR 2024
FD 2024-08
LK https://uvadoc.uva.es/handle/10324/69758
UL https://uvadoc.uva.es/handle/10324/69758
LA eng
NO Producción Científica
NO Departamento de Informática
DS UVaDOC
RD 11-mar-2025