RT info:eu-repo/semantics/conferenceObject
T1 Automatic Run-time Mapping of Polyhedral Computations to Heterogeneous Devices with Memory-size Restrictions
A1 Torres de la Sierra, Yuri
A1 González Escribano, Arturo
A1 Llanos Ferraris, Diego Rafael
K1 Informática
K1 Heterogeneous devices
K1 Polyhedral model
K1 Memory-size restrictions
K1 Automatic mapping tools
K1 1203 Ciencia de Los Ordenadores
K1 3304 Tecnología de Los Ordenadores
AB Tools that aim to automatically map parallel computations to heterogeneous and hierarchical systems try to divide the whole computation in parts with computational loads adjusted to the capabilities of the target devices. Some parts are executed in node cores, while others are executed in accelerator devices. Each part requires one or more data-structure pieces that should be allocated in the device memory during the computation. In this paper we present a model that allows such automatic mapping tools to transparently assign computations to heterogeneous devices with different memory size restrictions. The model requires the programmer to specify the access patterns of the computation threads in a simple abstract form. This information is used at run-time to determine the second-level partition of the computation assigned to a device, ensuring that the data pieces required by each sub-part fit in the target device memory, and that the number of kernels launched is minimal. We present experimental results with a prototype implementation of the model that works for regular polyhedral expressions. We show how it works for different example applications and access patterns, transparently executing big computations in devices with different memory size restrictions.
YR 2013
FD 2013
LK https://uvadoc.uva.es/handle/10324/70522
UL https://uvadoc.uva.es/handle/10324/70522
LA eng
NO Parallel and Distributed Processing Techniques and Applications (PDPTA 2013), Las Vegas, Nevada
NO Producción Científica
DS UVaDOC
RD 23-nov-2024