RT info:eu-repo/semantics/conferenceObject
T1 Understanding the Impact of CUDA Tuning Techniques for Fermi
A1 Torres de la Sierra, Yuri
A1 González Escribano, Arturo
A1 Llanos Ferraris, Diego Rafael
K1 Informática
K1 GPU, Fermi, performance, code tuning
K1 1203 Ciencia de Los Ordenadores
K1 3304 Tecnología de Los Ordenadores
AB While the correctness of an NVIDIA CUDA program is easy to achieve, exploiting the GPU capabilities to obtain the best performance possible is a task for CUDA experienced programmers. Typical code tuning strategies, like choosing an appropriate size and shape for the thread blocks, programming a good coalescing, or maximize occupancy, are inter-dependent. Moreover, the choices are also dependent on the underlying architecture details, and the global-memory access pattern of the designed solution. For example, the size and shapes of threadblocks are usually chosen to facilitate encoding (e.g. square shapes), while maximizing the multiprocessors' occupancy. How ever, this simple choice does not usually provide the best performance results. In this paper we discuss important relations between the size and shapes of threadblocks, occupancy, global memory access patterns, and other Fermi architecture features, such as the configuration of the new transparent cache. We present an insight based approach to tuning techniques, providing lines to understand the complex relations, and to easily avoid bad tuning settings.
SN 978-1-61284-383-4
YR 2011
FD 2011
LK https://uvadoc.uva.es/handle/10324/75305
UL https://uvadoc.uva.es/handle/10324/75305
LA eng
NO 2011 International Conference on High Performance Computing and Simulation (HPCS),  Istanbul, Turkey, July 4-8 2011  Istambul, Turkey
NO Producción Científica
DS UVaDOC
RD 24-abr-2025