TY  - GEN 
AU  - Milo, V.
AU  - Anzalone, F.
AU  - Zambelli, C.
AU  - Pérez, E.
AU  - Mahadevaiah, M.K.
AU  - González Ossorio, Óscar
AU  - Olivo, P.
AU  - Wenger, Christian
AU  - Ielmini, D.
PY  - 2021
SN  - 978-1-7281-6893-7
UR  - https://uvadoc.uva.es/handle/10324/66068
AB  - A key requirement for RRAM in neural network accelerators with a large number of synaptic parameters is the multilevel programming. This is hindered by resistance imprecision due to cycle-to-cycle and device-to-device variations. Here, we compare two...
LA  - eng
PB  - Institute of Electrical and Electronics Engineers
KW  - Resistive-switching random access memory (RRAM)
KW  - Multilevel programming
KW  - Resistance variability
KW  - Weight quantization
KW  - Hardware neural networks
KW  - In-memory computing
TI  - Optimized programming algorithms for multilevel RRAM in hardware neural networks
DO  - 10.1109/IRPS46558.2021.9405119
ER  -