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Título
Reliability of Logic-in-Memory Circuits in Resistive Memory Arrays
Autor
Año del Documento
2020
Editorial
Institute of Electrical and Electronics Engineers
Descripción
Producción Científica
Documento Fuente
IEEE Transactions on Electron Devices, 2020, Volume 67, Issue: 11
Resumo
Logic-in-memory (LiM) circuits based on resistive random access memory (RRAM) devices and the material implication logic are promising candidates for the development of low-power computing devices that could fulfill the growing demand of distributed computing systems. However, these circuits are affected by many reliability challenges that arise from device nonidealities (e.g., variability) and the characteristics of the employed circuit architecture. Thus, an accurate investigation of the variability at the array level is needed to evaluate the reliability and performance of such circuit architectures. In this work, we explore the reliability and performance of smart IMPLY (SIMPLY) (i.e., a recently proposed LiM architecture with improved reliability and performance) on two 4-kb RRAM arrays based on different resistive switching oxides integrated in the back end of line (BEOL) of the 0.25-μm BiCMOS process. We analyze the tradeoff between reliability and energy consumption of SIMPLY architecture by exploiting the results of an extensive array-level variability characterization of the two technologies. Finally, we study the worst case performance of a full adder implemented with the SIMPLY architecture and benchmark it on the analogous CMOS implementation.
Palabras Clave
Memoria RAM resistiva (RRAM)
Resistive RAM memory (RRAM)
ISSN
0018-9383
Revisión por pares
SI
Patrocinador
European Union’s Horizon 2020 Research and Innovation Programme under Grant 648635
Patrocinador
info:eu-repo/grantAgreement/EC/H2020/648635
Version del Editor
Propietario de los Derechos
© 2020 IEEE
Idioma
eng
Tipo de versión
info:eu-repo/semantics/acceptedVersion
Derechos
openAccess
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