Monolithic integration of InP nanowires with CMOS fabricated silicon nanotips wafer

Abstract

The integration of both optical and electronic components on a single chip, despite several challenges, holds the promise of compatibility with complementary metal-oxide semiconductor (CMOS) technology and high scalability. Among all candidate materials, III-V semiconductors exhibit great potential for optoelectronics and quantum-optics based devices, such as light emitters and harvesters. The control over geometry, and dimensionality of the III-V nanostructures, enables one to modify the band structures, and hence provide a powerful tool for tailoring the optoelectronic properties of III-V compounds. One of the most creditable approaches towards such growth control is the combination of using a patterned wafer and the self-assembled epitaxy. This work presents monolithically integrated catalyst-free InP nanowires grown selectively on Si nanotip-patterned, CMOS compatible (001) Si substrates using gas-source molecular-beam epitaxy. We use nanoheteroepitaxy approach to selectively grow InP nanowires on Si nanotips, which holds benefits due to its peculiar substrate design. In addition, our methodology allows the switching of dimensionality of the InP structures between one-dimensional nanowires and three-dimensional bulklike InP nanoislands by thermally modifying the shape of silicon nanotips surrounded by the silicon dioxide layer during the thermal cleaning of the substrate. The structural and optical characterization of nanowires indicates the coexistence of both zincblende and wurtzite InP crystal phases in nanowires. The two different crystal structures were aligned with a type-II band alignment. The luminescence from InP nanowires was measured up to 300 K, which reveals their promising optical quality for integrated photonics and optoelectronic applications.