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    Por favor, use este identificador para citar o enlazar este ítem:https://uvadoc.uva.es/handle/10324/75870

    Título
    Comparing Portability of FPGA High-Level Synthesis Frameworks in the Context of a Highly-Parallel Application
    Autor
    De Castro, Manuel
    Osorio, Roberto R.
    Andújar, Francisco J.
    Carratalá-Sáez, Rocío
    Torres, Yuri
    Llanos, Diego R.
    Año del Documento
    2025
    Editorial
    IEEE
    Descripción
    Producción Científica
    Documento Fuente
    M. De Castro, R. R. Osorio, F. J. Andújar, R. Carratalá-Sáez, Y. Torres and D. R. Llanos, "Comparing Portability of FPGA High-Level Synthesis Frameworks in the Context of a Highly-Parallel Application," in IEEE Access, vol. 13, pp. 50394-50410, 2025, doi: 10.1109/ACCESS.2025.3551428
    Zusammenfassung
    With the growing popularity of FPGA-based accelerators in HPC applications, new challenges have emerged, particularly in terms of programming and portability. This paper provides an overview of the current state of FPGA tools and their limitations. This study evaluates the performance and portability of two frameworks, SYCL and OpenCL, for developing HPC FPGA solutions. The case of porting a highly-parallel application to FPGAs is studied. First, naïve, low-development-effort implementations are presented using both ND-range and single-task types of kernels, and their performance is evaluated. Subsequently, an optimized FPGA-centric approach is presented and assessed using metrics from the compilation framework. Finally, the different approaches presented are implemented using OpenCL and SYCL and their performance is evaluated. Results reveal that ND-range kernels offer high portability for highly parallel applications, while single-task codes exhibit significantly lower portability. Additionally, SYCL struggles to generate efficient hardware architectures for this kind of application when described as single-task codes, although its performance when following the ND-range approach is surprisingly high.
    Materias (normalizadas)
    Informática
    Materias Unesco
    1203 Ciencia de Los Ordenadores
    3304 Tecnología de Los Ordenadores
    Palabras Clave
    Data Parallelism, FPGA, HLS, OpenCL, Portability, SYCL
    ISSN
    2169-3536
    Revisión por pares
    SI
    DOI
    10.1109/ACCESS.2025.3551428
    Patrocinador
    This work was supported in part by: The Spanish Ministerio de Ciencia e Innovación and by the European Regional Development Fund (ERDF) program of the European Union, under Grant PID2022-142292NB-I00 (NATASHA Project); and in part by the Junta de Castilla y León - FEDER Grants, under Grant VA226P20 (PROPHET-2 Project), Junta de Castilla y León, Spain. This work was also supported in part by grant TED2021–130367B–I00, funded by MCIN/AEI/10.13039/ 501100011033 and by “European UnionNextGenerationEU/PRTR”, and by grant PID2022-136435NB-I00, funded by MCIN/AEI/ 10.13039/501100011033 and by “ERDF A way of making Europe”, EU. Manuel de Castro has been supported by Spanish Ministerio de Ciencia, Innovación y Universidades, through “Ayudas para la Formación de Profesorado Universitario FPU 2022”.
    Version del Editor
    https://ieeexplore.ieee.org/abstract/document/10926827
    Idioma
    eng
    URI
    https://uvadoc.uva.es/handle/10324/75870
    Tipo de versión
    info:eu-repo/semantics/publishedVersion
    Derechos
    openAccess
    Aparece en las colecciones
    • DEP41 - Artículos de revista [109]
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    Nombre:
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