Mostrar el registro sencillo del ítem

dc.contributor.authorDueñas Carazo, Salvador 
dc.contributor.authorCastán Lanaspa, María Helena 
dc.contributor.authorGonzález Ossorio, Óscar 
dc.contributor.authorGarcía García, Héctor 
dc.date.accessioned2021-01-26T12:30:37Z
dc.date.available2021-01-26T12:30:37Z
dc.date.issued2019
dc.identifier.citationMicroelectronic Engineering, 2019, vol. 216. 4 p.es
dc.identifier.issn0167-9317es
dc.identifier.urihttp://uvadoc.uva.es/handle/10324/45138
dc.descriptionProducción Científicaes
dc.description.abstractIn this work, we have characterized hafnium oxide based bipolar resistive switching memories (RRAM) by measuring the small-signal conductance. The samples under study exhibit a continuum of intermediate states which can be accurately controlled by means of adequate sequence of the applied stimulus. The experimental results are analyzed to obtain information on the dynamics of the set and reset processes. This study reveals that ON-to-OFF (reset) and OFF-to-ON (set) processes are not symmetrical. Set transition is gradual and depends on the voltage stimulus according to an Erlang function which consists of a sum of k independent and identically distributed mechanisms, each having an exponential distribution. In contrast, reset process is more abrupt and can be described by a sigmoidal law. Time dependencies of set and reset process at fixed voltage values are explored as well. Set process is gradual at any positive voltage, whereas reset process is characterized by a time constant which depends on the applied voltage. Experimental results are explained in terms of the formation of interfacial barrier between the top electrode and the conductive filament.es
dc.format.mimetypeapplication/pdfes
dc.language.isoenges
dc.publisherElsevieres
dc.rights.accessRightsinfo:eu-repo/semantics/openAccesses
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/4.0/*
dc.subject.classificationResistive switchinges
dc.subject.classificationConmutación resistivaes
dc.titleDynamics of set and reset processes on resistive switching memorieses
dc.typeinfo:eu-repo/semantics/articlees
dc.rights.holder© 2019 Elsevieres
dc.identifier.doi10.1016/j.mee.2019.111032es
dc.relation.publisherversionhttps://www.sciencedirect.com/science/article/pii/S0167931719301893?via%3Dihubes
dc.peerreviewedSIes
dc.description.projectMinisterio de Economía, Industria y Competitividad (project TEC2017-84321-C4-2-R)es
dc.rightsAttribution-NonCommercial-NoDerivatives 4.0 Internacional*
dc.type.hasVersioninfo:eu-repo/semantics/draftes


Ficheros en el ítem

Thumbnail

Este ítem aparece en la(s) siguiente(s) colección(ones)

Mostrar el registro sencillo del ítem