Por favor, use este identificador para citar o enlazar este ítem:https://uvadoc.uva.es/handle/10324/55695
Título
Energy efficient HPC network topologies with on/off links
Autor
Año del Documento
2022
Editorial
Elsevier
Descripción
Producción Científica
Documento Fuente
Future Generation Computer Systems, 2022, vol. 139, p. 126-138
Résumé
Energy efficiency is a must in today HPC systems. To achieve this goal, a holistic design based on the use of power-aware components should be performed. One of the key components of an HPC system is the high-speed interconnect. In this paper, we compare and evaluate several design options for the interconnection network of an HPC system, including torus, fat-trees and dragonflies. State of the art low power modes are also used in the interconnection networks. The paper does not only consider energy efficiency at the interconnection network level but also at the system as a whole.
The analysis is performed by using a simple yet realistic power model of the system. The model has been adjusted using actual power consumption values measured on a real system. Using this model, realistic multi-job trace-based workloads have been used, obtaining the execution time and energy consumed. The results are presented to ease choosing a system, depending on which parameter, performance or energy consumption, receives the most importance.
Materias Unesco
1203.17 Informática
Palabras Clave
Interconnection networks
Redes de interconexión
ISSN
0167-739X
Revisión por pares
SI
Patrocinador
Ministerio de Economía, Industria y Competitividad (projects PID2019-105903RB-100 and PID2021-123627OB)
Junta de Comunidades de Castilla-La Mancha (project SBPLY/21/180501/ 000248)
Junta de Comunidades de Castilla-La Mancha (project SBPLY/21/180501/ 000248)
Propietario de los Derechos
© 2022 The Authors
Idioma
eng
Tipo de versión
info:eu-repo/semantics/publishedVersion
Derechos
openAccess
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