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dc.contributor.author | García García, Héctor | |
dc.contributor.author | González Ossorio, Óscar | |
dc.contributor.author | Dueñas Carazo, Salvador | |
dc.contributor.author | Castán Lanaspa, María Helena | |
dc.date.accessioned | 2021-02-25T12:20:08Z | |
dc.date.available | 2021-02-25T12:20:08Z | |
dc.date.issued | 2019 | |
dc.identifier.citation | Microelectronic Engineering, 2019, vol. 215. 14 p. | es |
dc.identifier.issn | 0167-9317 | es |
dc.identifier.uri | http://uvadoc.uva.es/handle/10324/45394 | |
dc.description | Producción Científica | es |
dc.description.abstract | RRAM devices are promising candidates to implement artificial synaptic devices for their use in neuromorphic systems, due to their high number or reachable conductance levels. The capacitors used in this work (TiN/Ti/ HfO2/W) show resistive switching behavior and reachable intermediate conductance states. We can control the conductance states by applying voltage pulses to the top electrode. Different approaches to control the synaptic weight have been studied: applying pulses with different voltage amplitudes changes the synaptic weight variation in an exponential way, and applying pulses with different lengths changes the synaptic weight in a linear way. We can control the conductance values when applying depression pulses, but the potentiation characteristic is not linear, as for other synaptic devices, as PRAMs. Applying other voltage signals to the structure, as voltage ramps, can improve the potentiation characteristic. | es |
dc.format.mimetype | application/pdf | es |
dc.language.iso | eng | es |
dc.publisher | Elsevier | es |
dc.rights.accessRights | info:eu-repo/semantics/openAccess | es |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/4.0/ | * |
dc.subject.classification | Resistive memories | es |
dc.subject.classification | Memorias resistivas | es |
dc.subject.classification | Synaptic devices | es |
dc.subject.classification | Dispositivos sinápticos | es |
dc.title | Controlling the intermediate conductance states in RRAM devices for synaptic applications | es |
dc.type | info:eu-repo/semantics/article | es |
dc.rights.holder | © 2019 Elsevier | es |
dc.identifier.doi | 10.1016/j.mee.2019.110984 | es |
dc.relation.publisherversion | https://www.sciencedirect.com/science/article/abs/pii/S0167931719301376 | es |
dc.peerreviewed | SI | es |
dc.description.project | Ministerio de Economía, Ciencia y Competitividad - Fondo Europeo de Desarrollo Regional (project TEC2017-84321-C4-2-R) | es |
dc.rights | Attribution-NonCommercial-NoDerivatives 4.0 Internacional | * |
dc.type.hasVersion | info:eu-repo/semantics/acceptedVersion | es |
dc.subject.unesco | 3307.90 Microelectrónica | es |
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