Rapid thermal process driven intra-die device variations

Abstract

Intra-die device variation due to pattern layout effects associated with the development of ultra-fast annealing processes is one of the major scaling challenges for advanced CMOS devices. In this paper, we show that an excellent and universal correlation can be established between on-die device variation and a new reflectance characterization technique with sufficient resolution. This approach has the potential to be universally applicable to virtually any structure pattern. In addition, we conducted simulations of the thermal annealing effect on 2D doping profiles by considering the effects of temperature sensitivity, reflectivity, and active dopant fraction. Our results show that the observed on-die variation was caused mainly by using a rapid thermal annealing (RTA) process rather than by flash annealing (FLA). We further concluded that pattern-induced device variation is mainly due to the redistribution of the dopants, instead of from dopant activation. To mitigate the pattern loading effect from thermal annealing, we employed a light absorbing layer to eliminate the within-die reflectivity variation. We found that we could successfully reduce electrical on-die variation by 50%.