Optimized programming algorithms for multilevel RRAM in hardware neural networks

Milo, V.; Anzalone, F.; Zambelli, C.; Pérez, E.; Mahadevaiah, M.K.; González Ossorio, Óscar; Olivo, P.; Wenger, Christian; Ielmini, D.

doi:10.1109/IRPS46558.2021.9405119

Por favor, use este identificador para citar o enlazar este ítem:https://uvadoc.uva.es/handle/10324/66068

Título

Optimized programming algorithms for multilevel RRAM in hardware neural networks

Autor

González Ossorio, Óscar

Olivo, P.

Wenger, Christian

Ielmini, D.

Congreso

2021 IEEE International Reliability Physics Symposium (IRPS)

Año del Documento

2021

Editorial

Institute of Electrical and Electronics Engineers

Descripción Física

Descripción

Producción Científica

Documento Fuente

2021 IEEE International Reliability Physics Symposium (IRPS), Monterey, CA, USA, 2021, p. 1-6

Résumé

A key requirement for RRAM in neural network accelerators with a large number of synaptic parameters is the multilevel programming. This is hindered by resistance imprecision due to cycle-to-cycle and device-to-device variations. Here, we compare two multilevel programming algorithms to minimize resistance variations in a 4-kbit array of HfO 2 RRAM. We show that gate-based algorithms have the highest reliability. The optimized scheme is used to implement a neural network with 9-level weights, achieving 91.5% (vs. software 93.27%) in MNIST recognition.

Palabras Clave

Resistive-switching random access memory (RRAM)

Multilevel programming

Resistance variability

Weight quantization

Hardware neural networks

In-memory computing

ISBN

978-1-7281-6893-7

DOI

10.1109/IRPS46558.2021.9405119

Version del Editor